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https://github.com/TomHarte/CLK.git
synced 2026-04-21 02:17:08 +00:00
Promote DigitalPhaseLockedLoop to a template, simplify to O(1) add_pulse.
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@@ -15,10 +15,10 @@ using namespace Storage::Disk;
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Controller::Controller(Cycles clock_rate) :
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clock_rate_multiplier_(128000000 / clock_rate.as_integral()),
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clock_rate_(clock_rate.as_integral() * clock_rate_multiplier_),
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pll_(100),
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empty_drive_(new Drive(int(clock_rate.as_integral()), 1, 1)) {
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// seed this class with a PLL, any PLL, so that it's safe to assume non-nullptr later
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Time one(1);
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set_expected_bit_length(one);
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pll_.set_delegate(this);
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set_expected_bit_length(Time(1));
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set_drive(empty_drive_);
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}
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@@ -42,13 +42,13 @@ Drive &Controller::get_drive() {
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void Controller::process_event(const Drive::Event &event) {
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switch(event.type) {
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case Track::Event::FluxTransition: pll_->add_pulse(); break;
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case Track::Event::FluxTransition: pll_.add_pulse(); break;
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case Track::Event::IndexHole: process_index_hole(); break;
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}
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}
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void Controller::advance(const Cycles cycles) {
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if(is_reading_) pll_->run_for(Cycles(cycles.as_integral() * clock_rate_multiplier_));
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if(is_reading_) pll_.run_for(Cycles(cycles.as_integral() * clock_rate_multiplier_));
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}
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void Controller::process_write_completed() {
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@@ -66,9 +66,8 @@ void Controller::set_expected_bit_length(Time bit_length) {
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// this conversion doesn't need to be exact because there's a lot of variation to be taken
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// account of in rotation speed, air turbulence, etc, so a direct conversion will do
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int clocks_per_bit = cycles_per_bit.get<int>();
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pll_ = std::make_unique<DigitalPhaseLockedLoop>(clocks_per_bit, 3);
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pll_->set_delegate(this);
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const int clocks_per_bit = cycles_per_bit.get<int>();
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pll_.set_clocks_per_bit(clocks_per_bit);
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}
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void Controller::digital_phase_locked_loop_output_bit(int value) {
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