mirror of
https://github.com/TomHarte/CLK.git
synced 2024-11-26 23:52:26 +00:00
Be overt about the size being described here.
This commit is contained in:
parent
5db0ea0236
commit
fed79a116f
@ -497,7 +497,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
|
||||
op1_mode, op1_reg,
|
||||
op2_mode, op2_reg,
|
||||
requires_supervisor<model>(operation),
|
||||
size(operation),
|
||||
operand_size(operation),
|
||||
condition);
|
||||
}
|
||||
|
||||
@ -510,7 +510,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
|
||||
op1_mode, op1_reg,
|
||||
op2_mode, op2_reg,
|
||||
requires_supervisor<model>(operation),
|
||||
size(operation),
|
||||
operand_size(operation),
|
||||
condition);
|
||||
}
|
||||
|
||||
|
@ -114,7 +114,7 @@ typename Executor<model, BusHandler>::EffectiveAddress Executor<model, BusHandle
|
||||
ea.requires_fetch = false;
|
||||
break;
|
||||
case AddressingMode::ImmediateData:
|
||||
switch(instruction.size()) {
|
||||
switch(instruction.operand_size()) {
|
||||
case DataSize::Byte:
|
||||
ea.value.l = read_pc<uint16_t>() & 0xff;
|
||||
break;
|
||||
@ -153,7 +153,7 @@ typename Executor<model, BusHandler>::EffectiveAddress Executor<model, BusHandle
|
||||
ea.value = registers_[8 + reg];
|
||||
ea.requires_fetch = true;
|
||||
|
||||
switch(instruction.size()) {
|
||||
switch(instruction.operand_size()) {
|
||||
case DataSize::Byte: registers_[8 + reg].l += byte_increments[reg]; break;
|
||||
case DataSize::Word: registers_[8 + reg].l += 2; break;
|
||||
case DataSize::LongWord: registers_[8 + reg].l += 4; break;
|
||||
@ -162,7 +162,7 @@ typename Executor<model, BusHandler>::EffectiveAddress Executor<model, BusHandle
|
||||
case AddressingMode::AddressRegisterIndirectWithPredecrement: {
|
||||
const auto reg = instruction.reg(index);
|
||||
|
||||
switch(instruction.size()) {
|
||||
switch(instruction.operand_size()) {
|
||||
case DataSize::Byte: registers_[8 + reg].l -= byte_increments[reg]; break;
|
||||
case DataSize::Word: registers_[8 + reg].l -= 2; break;
|
||||
case DataSize::LongWord: registers_[8 + reg].l -= 4; break;
|
||||
@ -255,9 +255,9 @@ void Executor<model, BusHandler>::run_for_instructions(int count) {
|
||||
const auto flags = operand_flags<model>(instruction.operation);
|
||||
|
||||
// TODO: potential alignment exception, here and in store.
|
||||
#define fetch_operand(n) \
|
||||
if(effective_address_[n].requires_fetch) { \
|
||||
read(instruction.size(), effective_address_[n].value.l, operand_[n]); \
|
||||
#define fetch_operand(n) \
|
||||
if(effective_address_[n].requires_fetch) { \
|
||||
read(instruction.operand_size(), effective_address_[n].value.l, operand_[n]); \
|
||||
}
|
||||
|
||||
if(flags & FetchOp1) { fetch_operand(0); }
|
||||
@ -268,15 +268,15 @@ void Executor<model, BusHandler>::run_for_instructions(int count) {
|
||||
perform<model>(instruction, operand_[0], operand_[1], status_, *this);
|
||||
|
||||
// TODO: rephrase to avoid conditional below.
|
||||
#define store_operand(n) \
|
||||
if(!effective_address_[n].requires_fetch) { \
|
||||
if(instruction.mode(n) == AddressingMode::DataRegisterDirect) { \
|
||||
registers_[instruction.reg(n)] = operand_[n]; \
|
||||
} else { \
|
||||
registers_[8 + instruction.reg(n)] = operand_[n]; \
|
||||
} \
|
||||
} else { \
|
||||
write(instruction.size(), effective_address_[n].value.l, operand_[n]); \
|
||||
#define store_operand(n) \
|
||||
if(!effective_address_[n].requires_fetch) { \
|
||||
if(instruction.mode(n) == AddressingMode::DataRegisterDirect) { \
|
||||
registers_[instruction.reg(n)] = operand_[n]; \
|
||||
} else { \
|
||||
registers_[8 + instruction.reg(n)] = operand_[n]; \
|
||||
} \
|
||||
} else { \
|
||||
write(instruction.operand_size(), effective_address_[n].value.l, operand_[n]); \
|
||||
}
|
||||
|
||||
if(flags & StoreOp1) { store_operand(0); }
|
||||
|
@ -131,7 +131,7 @@ enum class DataSize {
|
||||
/// For any operations that don't fit the neat model of reading one or two operands,
|
||||
/// then writing zero or one, the size determines the data size of the operands only,
|
||||
/// not any other accesses.
|
||||
constexpr DataSize size(Operation operation) {
|
||||
constexpr DataSize operand_size(Operation operation) {
|
||||
switch(operation) {
|
||||
// These are given a value arbitrarily, to
|
||||
// complete the switch statement.
|
||||
@ -510,7 +510,7 @@ class Preinstruction {
|
||||
bool requires_supervisor() const {
|
||||
return flags_ & 0x80;
|
||||
}
|
||||
DataSize size() const {
|
||||
DataSize operand_size() const {
|
||||
return DataSize(flags_ & 0x03);
|
||||
}
|
||||
Condition condition() const {
|
||||
|
Loading…
Reference in New Issue
Block a user