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Commit Graph

157 Commits

Author SHA1 Message Date
Thomas Harte
058fe3e986 Fixes some other low-hanging warning fruit. 2019-06-04 16:47:10 -04:00
Thomas Harte
51ee83a427 Resolves a further 11 conversion errors. 2019-06-04 16:34:45 -04:00
Thomas Harte
5b21da7874 Reduces number of warnings to 70. 2019-06-04 16:27:09 -04:00
Thomas Harte
bd7f00bd9c Resolves a further handful of implicit type conversion warnings. 2019-06-04 15:43:44 -04:00
Thomas Harte
4d4ddded6d Fixes register-relative JMP and JSR. 2019-06-03 15:29:50 -04:00
Thomas Harte
881feb1bd3 Adds preliminary parsing of the Disk Copy 4.2 format. 2019-06-02 13:39:25 -04:00
Thomas Harte
b3d2b4cd37 Fixes the interrupt return address. 2019-05-29 20:27:46 -04:00
Thomas Harte
ecf93b7822 Eliminates some type conversion warnings. 2019-05-29 14:56:50 -04:00
Thomas Harte
541b75ee6e Further fixes PEA, and OR/AND/EOR Dn, (An). 2019-05-29 14:37:15 -04:00
Thomas Harte
77b08febdb Corrects PEA and adds an additional debugging aid. 2019-05-29 12:47:17 -04:00
Thomas Harte
fcda376f33 Removes three further type conversion warnings. 2019-05-28 21:56:49 -04:00
Thomas Harte
0848fc7e03 Ensures the Mac uses auto vectored interrupts. 2019-05-28 16:24:41 -04:00
Thomas Harte
3bb8d6717f Ensures A7 is correct at end of an UNLINK. 2019-05-28 16:02:42 -04:00
Thomas Harte
c52da9d802 Adds some logging preparatory to a MOVE change. 2019-05-28 15:05:42 -04:00
Thomas Harte
249b0fbb32 Corrects PC on stack after an illegal instruction.
Also fixed LOG_TRACE functionality.
2019-05-08 22:36:25 -04:00
Thomas Harte
d8ed8b66f3 Improves carry/extend for ROXL and ROXR. 2019-05-06 21:14:16 -04:00
Thomas Harte
417a3e1540 Adds missing call to flush. 2019-05-03 23:31:12 -04:00
Thomas Harte
fa8c804d47 Makes explicit a few implicit type conversions.
There's plenty more down this well, alas.
2019-05-03 23:26:03 -04:00
Thomas Harte
0ea4c1ac80 Evicts #includes from my namespace. 2019-05-03 14:48:39 -04:00
Thomas Harte
cc8a65780e Adds further missing includes. 2019-05-03 14:42:36 -04:00
Thomas Harte
c117deb43b Introduces a couple of missing #includes. 2019-05-03 14:37:05 -04:00
Thomas Harte
a0eb20ff1f Tweaks divide-by-zero timing. 2019-05-03 14:29:36 -04:00
Thomas Harte
291e91375f Takes a shot at the synchronous bus. 2019-05-03 14:20:59 -04:00
Thomas Harte
857f74b320 Fixed: the accepted interrupt level now appears on the bus. 2019-05-02 15:47:12 -04:00
Thomas Harte
93616a4903 Completes test of a vectored interrupt.
Correcting issues uncovered.
2019-05-02 00:00:09 -04:00
Thomas Harte
bb07206c55 Corrects internet response to work as currently implemented.
Also makes corrections to the bus error and address error exceptions.
2019-05-01 21:59:06 -04:00
Thomas Harte
2e5c0811e7 Makes some effort at getting into interrupt processing. 2019-05-01 15:26:36 -04:00
Thomas Harte
f6ac407e4d Takes further steps towards supporting interrupts.
Specifically:
* introduces the necessary bus signalling; and
* adds corresponding functional steps.

Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 15:19:24 -04:00
Thomas Harte
92568c90c8 Adds support for HALT as an input, and puts some effort into how to calculate E. 2019-04-30 22:07:48 -04:00
Thomas Harte
f1879c5fbc Corrects interrupt level test within STOP. 2019-04-30 19:32:35 -04:00
Thomas Harte
31bb770fdd Implement STOPpages, waits for DTack, and bus and address error exceptions. 2019-04-30 19:24:22 -04:00
Thomas Harte
e430f2658f Adds a test and by that means fixes divide-by-zero exception return addresses. 2019-04-29 23:09:50 -04:00
Thomas Harte
977f9ee831 Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time. 2019-04-29 22:08:16 -04:00
Thomas Harte
16fb3b49a5 It leads to a TODO, but implemented decoding and initial setup of STOPpages. 2019-04-29 19:30:00 -04:00
Thomas Harte
bc00856c05 Removed TODO; it appears this is just the standard stack frame. 2019-04-29 19:09:20 -04:00
Thomas Harte
52e3dece81 Improves exposition. 2019-04-29 19:07:14 -04:00
Thomas Harte
2c1d8fa18a Adds a check for instruction privilege violation, albeit that I think I need different bus steps. 2019-04-29 19:06:10 -04:00
Thomas Harte
3e34ae67f6 Implements support for the trace flag. 2019-04-29 19:02:59 -04:00
Thomas Harte
ceebecec8d Corrects zero and negative flags for EXT.w. 2019-04-29 17:54:33 -04:00
Thomas Harte
270f46e147 Normalises CMPl. 2019-04-29 17:27:56 -04:00
Thomas Harte
8564945713 Corrects vector nomination for unrecognised opcodes. 2019-04-29 17:10:33 -04:00
Thomas Harte
7bd7f3fb73 Sign-extends (xxx).w addresses. 2019-04-29 16:55:43 -04:00
Thomas Harte
c466b6f9e7 Factors out the [unit testing] stuff of being a trace-checking 68000 bus handler. 2019-04-29 16:11:01 -04:00
Thomas Harte
d9071ee9f1 Starts sketching out the asynchronous bus. 2019-04-29 13:45:53 -04:00
Thomas Harte
ca1f669e64 Implements MOVEP.
371 is now the alleged number of missing opcodes. But I'd dare imagine it's more like three or four.
2019-04-28 22:52:54 -04:00
Thomas Harte
0298b1b3b7 Implements LINK and UNLINK.
Also starts excluding opcodes that I can't determine the mapping of from the list of those tested against.

Due to those two things together, the latter incomplete: 627 opcodes outstanding. But only STOP and MOVEP remain on my list of things to implement prior to exceptions.
2019-04-28 17:12:31 -04:00
Thomas Harte
4b1324de77 Takes a run at TRAPV.
... to leave 1466 as the unimplemented count.
2019-04-28 15:52:58 -04:00
Thomas Harte
8e8dce9bec Attempts an implementation of CHK.
1467 is now the official count of things to implement, though I'm starting to get suspicious.
2019-04-28 15:47:21 -04:00
Thomas Harte
f4350522bf Implements NBCD.
Now outstanding: 1891.
2019-04-27 21:29:50 -04:00
Thomas Harte
ab5fcab9bf Attempts an implementation of ADDX and SUBX.
Leaving 2005 non-[A/F]-line instructions.
2019-04-27 16:57:47 -04:00