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Commit Graph

611 Commits

Author SHA1 Message Date
Thomas Harte
e1a2580b2a Renamed BusOperation to MachineCycle::Operation. 2017-06-17 21:53:45 -04:00
Thomas Harte
b6f51474ff Ensured that -description can handle the newly-captured bus actions. 2017-06-17 18:20:30 -04:00
Thomas Harte
0f18768091 Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do. 2017-06-17 18:19:25 -04:00
Thomas Harte
50cd617bd9 Ensured test raises only the intentional failure exceptions. 2017-06-15 22:33:46 -04:00
Thomas Harte
838b818cd3 Finished transcribing first page of machine cycle documentation; several failures contained. 2017-06-15 22:19:49 -04:00
Thomas Harte
cf795562bf Continued filling in tests, fleshing out what the test machine captures as a result. 2017-06-15 20:59:59 -04:00
Thomas Harte
ac37424878 Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on. 2017-06-15 19:06:59 -04:00
Thomas Harte
aed2827e7b Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected. 2017-06-12 22:22:00 -04:00
Thomas Harte
a48616a138 Fixed reference to Swift-world MachineDocument for the ZX81 file type. 2017-06-12 18:51:11 -04:00
Thomas Harte
8222aac9e3 Added an official declaration of support for ZX81 files. 2017-06-11 21:40:41 -04:00
Thomas Harte
77aa3c187e Rebranded ZX80O as ZX80O81P, with an eye to making it accept ZX81 .p files. Adjusted the initial selection part of the static analyser appropriately. 2017-06-11 21:38:32 -04:00
Thomas Harte
8116f85479 Allowed the static analyser to specify a ZX80 or 81, and a memory model. Neither is respected yet in the machine. 2017-06-11 19:12:20 -04:00
Thomas Harte
50be3a24fe Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be. 2017-06-11 13:30:08 -04:00
Thomas Harte
7e10c7f9d8 Relocated the ZX80/81 concept of a 'file' out from Tape into Data, given that it's an exact duplicate of memory. 2017-06-08 19:09:51 -04:00
Thomas Harte
60300851ea Started sketching out a tape parser for ZX80 and '81 files. I think this'll help me to verify whether the .O input is working. 2017-06-07 10:12:13 -04:00
Thomas Harte
8c66e1d99d Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data. 2017-06-06 17:53:23 -04:00
Thomas Harte
cc4cb45e9d Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court. 2017-06-06 09:25:18 -04:00
Thomas Harte
c485c460f7 Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world. 2017-06-04 18:08:35 -04:00
Thomas Harte
b0a7c58287 Fixed project to point to the XIB I actually want to keep; fixed that XIB to have the correct contents. 2017-06-04 17:57:37 -04:00
Thomas Harte
d2637123c4 Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software. 2017-06-04 17:55:19 -04:00
Thomas Harte
02b7c3d1b0 Added the necessary wiring to get into a ZX80/81-oriented part of the static analyser, which could in principle post a ZX80 target. 2017-06-04 17:04:06 -04:00
Thomas Harte
8c1769f157 Made a quick attempt at serialising from ZX80 .O to waves. 2017-06-04 16:59:26 -04:00
Thomas Harte
655809517c Ensured that there is a subclass of file that is entrusted to load .O/.80 files, and that the code routes such files to it, noting that it should consider whether a ZX80 is required. 2017-06-04 16:37:03 -04:00
Thomas Harte
2190f60a89 Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool. 2017-06-04 15:46:35 -04:00
Thomas Harte
0eebfdb4cc Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines. 2017-06-04 15:39:37 -04:00
Thomas Harte
7811374b0f Started sneaking in memptr emulation, hopefully to get to a working BIT (hl). 2017-06-04 15:07:07 -04:00
Thomas Harte
87095b0578 Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures. 2017-06-04 14:04:26 -04:00
Thomas Harte
b642d9f712 Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs. 2017-06-03 21:54:42 -04:00
Thomas Harte
fd6623b5a5 Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502. 2017-06-03 21:22:16 -04:00
Thomas Harte
b304c3a4b9 Eliminated the 6502's reliance on the micro-op scheduler. 2017-06-03 20:30:07 -04:00
Thomas Harte
b3da16911f Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2. 2017-06-03 18:42:54 -04:00
Thomas Harte
e52892f75b Added a test of interrupt mode 1. 2017-06-03 18:16:13 -04:00
Thomas Harte
8c41a0f0ed Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine. 2017-06-03 17:53:44 -04:00
Thomas Harte
3e9212aaff Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed. 2017-06-03 17:41:45 -04:00
Thomas Harte
d14902700a Minor syntax and wiring fixes. 2017-06-01 22:33:05 -04:00
Thomas Harte
c95c32a9fe Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine. 2017-06-01 22:31:04 -04:00
Thomas Harte
494ce073b5 Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging. 2017-05-31 19:58:57 -04:00
Thomas Harte
5ff73faf48 Ensured Zexall can pass. 2017-05-31 19:55:06 -04:00
Thomas Harte
2f7f11e2e5 Added diagnosis props. 2017-05-31 06:54:25 -04:00
Thomas Harte
5119997122 Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function. 2017-05-30 22:41:23 -04:00
Thomas Harte
7bddd294c9 Resolved an unpredictable conditional and temporarily disabled the Zexalltest as part of the default suite, since it takes so long to run. 2017-05-30 21:03:02 -04:00
Thomas Harte
244b5ba3c2 Added a proper termination condition for Zexall and, for now, a Mhz counter. 2017-05-30 18:32:38 -04:00
Thomas Harte
960de7bd7b Marginally reduced test machine costs based on usage. 2017-05-30 11:59:07 -04:00
Thomas Harte
c6185baa99 Fixed R incrementation and attempted to make the status flags cheaper to write to. 2017-05-29 22:23:19 -04:00
Thomas Harte
4d4695032c Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end. 2017-05-29 21:46:00 -04:00
Thomas Harte
6d22f6fcd5 Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being. 2017-05-29 17:17:17 -04:00
Thomas Harte
8bfaa487ce Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit). 2017-05-29 17:13:24 -04:00
Thomas Harte
267b2add9a Adjusted for where FUSE nominally places timestamps. Down to 92 failures. 2017-05-29 16:44:07 -04:00
Thomas Harte
d290e3d99e Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!) 2017-05-29 16:35:00 -04:00
Thomas Harte
a6a4c5a936 Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures. 2017-05-29 15:57:27 -04:00