Thomas Harte
|
e1a2580b2a
|
Renamed BusOperation to MachineCycle::Operation.
|
2017-06-17 21:53:45 -04:00 |
|
Thomas Harte
|
aed2827e7b
|
Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
|
2017-06-12 22:22:00 -04:00 |
|
Thomas Harte
|
3e9212aaff
|
Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
|
2017-06-03 17:41:45 -04:00 |
|
Thomas Harte
|
d14902700a
|
Minor syntax and wiring fixes.
|
2017-06-01 22:33:05 -04:00 |
|
Thomas Harte
|
5119997122
|
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
|
2017-05-30 22:41:23 -04:00 |
|
Thomas Harte
|
da65bae86e
|
Switched to supplying the bus operation by reference, go guarantee that it isn't null.
|
2017-05-30 19:24:58 -04:00 |
|
Thomas Harte
|
9e25d014d2
|
Made an attempt to log bus activity for comparison with FUSE results.
|
2017-05-22 19:49:38 -04:00 |
|
Thomas Harte
|
41d5dd8679
|
Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
|
2017-05-22 19:24:11 -04:00 |
|
Thomas Harte
|
7190f927b7
|
Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
|
2017-05-16 21:28:17 -04:00 |
|
Thomas Harte
|
d559d8b901
|
Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
|
2017-05-16 21:19:17 -04:00 |
|