1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-25 16:31:42 +00:00
Commit Graph

13 Commits

Author SHA1 Message Date
Thomas Harte
4ee29b3266 Switches disk seeking logic fully to floating point. 2020-07-17 22:08:58 -04:00
Thomas Harte
25996ce180 Further doubles down on construction syntax for type conversions. 2020-05-09 23:00:39 -04:00
Thomas Harte
514141f8c5 Eliminates the optionality of a DPLL receiver. 2020-01-12 17:45:02 -05:00
Thomas Harte
f42655a0fc Promote DigitalPhaseLockedLoop to a template, simplify to O(1) add_pulse. 2020-01-12 17:25:21 -05:00
Thomas Harte
3633285aaa Ensures a trailing zero bit isn't dropped. 2019-07-16 16:36:00 -04:00
Thomas Harte
f75af3b45e Adds some extra exposition. 2018-07-01 14:41:17 -04:00
Thomas Harte
555c2a4377 Makes a first sweep at converting the storage underlying PCMSegment to vector<bool>.
This is to remove another pain point, in preparation for the work immediately forthcoming but also work as-yet unknown.
2018-07-01 12:05:41 -04:00
Thomas Harte
7cee3b7449 Resolves potential overflow / sign corruption. 2018-05-19 22:28:29 -04:00
Thomas Harte
8263c48a1d Added a guarantee that the TrackSerialiser won't modify tracks it receives. 2018-05-18 23:03:28 -04:00
Thomas Harte
0b771ce61a Removes all instances of the copyright symbol. 2018-05-13 15:19:52 -04:00
Thomas Harte
4c6dc597f4 Converts Time::get into a template, introduces a via-a-double fallback for the timed event loop. 2018-04-25 19:54:39 -04:00
Thomas Harte
ec999446e8 Commutes int and unsigned casts to the functional style. 2017-10-21 21:00:40 -04:00
Thomas Harte
9f4a407f94 Switches the track serialiser to a more standard header + implementation separation.
Also introduces a full priming of the PLL before deserialisation begins.
2017-09-26 22:01:32 -04:00