21 Commits

Author	SHA1	Message	Date
Thomas Harte	fbc273f114	Add invented model for tests.	2024-03-10 21:45:56 -04:00
Thomas Harte	a4cf86268e	Provide full access to stored registers.	2024-03-09 15:11:04 -05:00
Thomas Harte	fdef8901ab	Double down on uint32_t.	2024-03-08 14:13:34 -05:00
Thomas Harte	fa8fcd2218	Take another swing at popcount.	2024-03-07 14:28:31 -05:00
Thomas Harte	2a36d0fcbc	Adjust user-mode test.	2024-03-07 14:00:38 -05:00
Thomas Harte	0e92885ed5	Fix ad hoc popcount; ARM does carry 'backwards'.	2024-03-07 13:27:41 -05:00
Thomas Harte	a0f0f73bde	Fix MOV as unconditional branch.	2024-03-07 10:31:26 -05:00
Thomas Harte	108a056f1c	Execution now runs into a prefetch abort loop.	2024-03-06 15:05:24 -05:00
Thomas Harte	ba5f142515	Take further stab at TEQ PC, etc.	2024-03-05 10:55:44 -05:00
Thomas Harte	ed586e80bc	Don't write to the PC with logical operations.	2024-03-05 09:32:35 -05:00
Thomas Harte	230e9c6327	Obscure active.	2024-03-03 21:43:30 -05:00
Thomas Harte	11c4d2f09e	Add further exposition.	2024-03-03 21:38:27 -05:00
Thomas Harte	f2db1b4aae	Merge branch 'TiedDown' into PositiveExpression	2024-03-03 21:31:26 -05:00
Thomas Harte	b42a6e447d	Tie down more corners.	2024-03-03 21:29:53 -05:00
Thomas Harte	9fd7d5c10f	Switch test and meaning.	2024-03-03 14:34:21 -05:00
Thomas Harte	4e7963ee81	Clarify PC semantics; remove faulty underscore.	2024-03-03 14:11:02 -05:00
Thomas Harte	62da0dee7f	Unify reads.	2024-03-02 23:15:17 -05:00
Thomas Harte	1663d3d9d1	Introduce disaster of an attempted test run.	2024-03-02 22:40:12 -05:00
Thomas Harte	37499d493a	Fix model name.	2024-03-02 21:47:09 -05:00
Thomas Harte	e6f77a9b80	Add logical right-shift tests.	2024-03-01 18:06:54 -05:00
Thomas Harte	42ba6d1281	Relocate execution code appropriately.	2024-03-01 15:02:47 -05:00