28 Commits

Author	SHA1	Message	Date
Thomas Harte	31c6faf3c8	Adds a bunch of consts.	2020-05-09 21:23:52 -04:00
Thomas Harte	7cd11ecb7f	Adds necessary #include for assert.	2019-12-08 22:43:39 -05:00
Thomas Harte	acfe2c63b8	Adds an assert to verify the interrupt line is clear after a full reset.	2019-12-08 22:34:19 -05:00
Thomas Harte	b192381928	Implements a fuller reset, takes a run at the overran flag.	2019-12-08 21:20:06 -05:00
Thomas Harte	d6edfa5c6d	Removes the redundant state encased within interrupt_causes_.	2019-11-11 21:49:02 -05:00
Thomas Harte	072b0266af	It seems status reads are not required to clear the interrupt line.	2019-11-09 20:12:09 -05:00
Thomas Harte	8c736a639a	Eliminates unexpected bottleneck created by ACIA.	2019-11-09 15:00:12 -05:00
Thomas Harte	14e790746b	Fixes return value when reading received data.	2019-11-02 21:25:00 -04:00
Thomas Harte	1c154131f9	Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.	2019-10-29 22:36:29 -04:00
Thomas Harte	7cb82fccc0	Attempts properly to maintain interrupt flag; adds delegate.	2019-10-21 22:40:38 -04:00
Thomas Harte	ed9a5b0430	Adds receipt interrupt.	2019-10-21 21:27:57 -04:00
Thomas Harte	8f59a73425	Corrects incoming data capture.	2019-10-21 20:18:52 -04:00
Thomas Harte	83f5f0e2ad	Begins trying to receive ACIA data.	2019-10-21 20:10:19 -04:00
Thomas Harte	4134463094	The ACIA now receives bits.	2019-10-20 23:34:30 -04:00
Thomas Harte	cf07982a9b	Ensures good serial line and ACIA behaviour. ... Next stop: having the intelligent keyboard react.	2019-10-20 22:10:05 -04:00
Thomas Harte	696af5c3a6	Starts to transfer serial line decoding logic into the line itself.	2019-10-20 20:38:56 -04:00
Thomas Harte	9a8352282d	Mostly but not quite fixes serial work.	2019-10-20 20:38:55 -04:00
Thomas Harte	34075a7674	Attempts to tie an intelligent keyboard to the other end of its serial line.	2019-10-20 20:38:55 -04:00
Thomas Harte	c10b64e1c0	Adds a received_data_ register, that presently can never fill.	2019-10-20 20:38:55 -04:00
Thomas Harte	5d5fe52144	Corrects transmission logic — exactly hitting write_data_time_remaining now works properly.	2019-10-20 20:38:55 -04:00
Thomas Harte	ff62eb6dce	The ACIA actually has two clocks, though on an ST they're both 500,000 Hz.	2019-10-20 20:38:55 -04:00
Thomas Harte	374439693e	Ensures serial lines know their writer's clock rate.	2019-10-20 20:38:55 -04:00
Thomas Harte	c4ef33b23f	JustInTimeActors can now specify a clock divider.	2019-10-20 20:38:55 -04:00
Thomas Harte	a7ed357569	Attempts to implement transmission interrupts and ClockingHint::Source.	2019-10-20 20:38:55 -04:00
Thomas Harte	4e5b440145	Attempts mostly to implement 6850 output.	2019-10-20 20:38:55 -04:00
Thomas Harte	2bd7be13b5	Decodes the 6850 control register, and starts working on standardised serial ports.	2019-10-20 20:38:55 -04:00
Thomas Harte	4b09d7c41d	Nudges 6850 towards coherence.	2019-10-20 20:38:55 -04:00
Thomas Harte	4ead905c3c	Adds an empty shell for the ACIA.	2019-10-20 20:38:55 -04:00