00c32e4b59
Further miscellaneous changes to debug logging. All temporary.
2019-06-18 10:34:31 -04:00
877b46d2c1
Advances IWM/drive emulation very close to the point of 'Welcome to Macintosh'.
2019-06-15 16:08:54 -04:00
cc7226ae9f
Starts trying to get a bit more rigorous about collected meanings.
2019-06-13 22:48:10 -04:00
bde975a3b9
Possibly mights the tiniest bit of headway with 'the IWM'.
...
I'm now pretty sure that my 3.5" drive, which for now is implemented in the IWM (yuck) is just responding to queries incorrectly.
2019-06-13 22:38:09 -04:00
f6f9024631
Corrects Macintosh aspect ratio (and framing).
2019-06-13 18:41:38 -04:00
535747e3f2
Restores single-line logging format.
2019-06-13 13:35:03 -04:00
d6150645c0
By hook or by crook, mouse input now works.
2019-06-12 22:19:25 -04:00
ad8b68c998
Switches to a proper form of zero-upon-read data.
...
Not that it's necessarily correct.
2019-06-11 19:53:51 -04:00
3c075e9542
Switches drives 0 and 1.
2019-06-10 14:58:39 -04:00
50d37798a2
Eradicates magic constants.
2019-06-06 21:37:43 -04:00
e9d0676e75
Fiddles further with the tachometer.
2019-06-06 21:36:19 -04:00
7591906777
Numerous IWM fixes: the machine now seems to be trying to measure the tachometer.
2019-06-06 18:32:11 -04:00
a413ae11cb
Makes some sort of first attempt at having the IWM read.
2019-06-04 22:13:00 -04:00
b8a1553368
Adds putative support for PlusToo-style BIN files.
...
Albeit a bit of a guess, since it's not intended to be an emulator file format.
2019-06-04 21:41:09 -04:00
8557558bd8
Mildly improves investigatory reporting.
2019-06-03 21:51:45 -04:00
da2b190288
Stores expected bit length.
2019-06-01 19:08:29 -04:00
48d837c636
Attempts to respond more sensibly to various queries.
...
Including adding a 1-second delay on motor off.
2019-06-01 18:43:47 -04:00
723137c0d4
With some time additions to the 6522, starts wiring in Macintosh audio.
...
The audio buffer is also the disk motor buffer, so this is preparatory to further disk work.
2019-06-01 14:39:40 -04:00
4197c6f149
Attempts to make some further semantic sense of the various IWM controls.
2019-05-30 22:17:49 -04:00
4632be4fe5
Wires up the final IWM signal, SEL, preparatory to an implementation.
2019-05-30 12:08:00 -04:00
ce099a297a
Eliminates RAM writes in ROM area.
...
I no longer think that logic is correct.
2019-05-07 17:16:22 -04:00
96facc103a
Adds an IWM shim and corrects graphics output.
...
... now that there is some.
2019-05-05 21:55:34 -04:00
ee89be6730
Removes many stray spaces.
2018-11-23 22:32:32 -05:00
70c4d6b9b3
Adds a one second delay between controller and drive motor off.
2018-08-03 21:13:18 -04:00
98bb5bd9f1
Ensures flux bits are observable for two cycles rather than one; it should be 1us.
2018-07-31 23:01:11 -04:00
dde9b73a22
Creates the through-path that will be necessary for RWTS acceleration.
2018-06-09 12:51:53 -04:00
076fa55651
Corrects: flux set is no-flux incoming.
...
This restores good sleeping behaviour.
2018-06-03 08:11:17 -04:00
75f9e3caeb
Resolves incorrect bracketing.
2018-05-28 17:48:35 -04:00
928aab13dc
Introduces more granular clocking announcements to the Disk II.
...
As well as making it accept the clock rate it'll actually receive, to supply to the drives, so that they spin at the proper speed.
2018-05-28 17:19:29 -04:00
db8d8d8404
Commutes Sleeper to ClockingHint::Source, making state more granular.
2018-05-27 23:17:06 -04:00
086b801c29
Mildly rearranges to avoid unnecessary call.
2018-05-22 21:50:07 -04:00
e482929da8
Enhances the Disk II's ability to sleep.
...
Also enables Disk II sleep observation in the Oric.
2018-05-19 23:15:28 -04:00
ed06533e60
Implements write support out of the Disk II.
2018-05-18 22:07:58 -04:00
7b7beb13a3
Eliminates the fiction of setting and getting registers.
...
The Disk II seems lower level than that; it will read the data bus whenever it likes, it is the programmer's responsibility to keep up with that. It also reserves the right not to load the bus regardless of whether it receives a read or write access.
2018-05-17 21:39:11 -04:00
c46007332a
Switches to returning the shift register contents on every even read.
2018-05-17 20:18:34 -04:00
908d3b0ee5
Slightly wrong as to the details, but gets the controller trying to output.
...
At an initial look, I think the shift register should end up on the data bus for all odd accesses. Need to investigate more thoroughly.
2018-05-16 22:37:22 -04:00
8a031b1137
Eliminates 'data' register as it doesn't exist; rejigs state machine command set.
2018-05-16 22:09:59 -04:00
1aba9f807e
Ensures proper upward propagation of sleeping from first start.
2018-05-16 22:07:54 -04:00
4c49963988
Switches to proper handling of the motor control and write protection.
...
Per Understanding the Apple II the drive looks write protected while phase 1 is enabled.
2018-05-16 21:44:09 -04:00
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
d703328114
Adds missing #include for memcpy.
2018-05-12 17:54:13 -04:00
a43ca0db35
Makes the Apple II an activity source.
2018-05-10 22:17:13 -04:00
c3144382c5
Shuffles the Disk II ROM at load time into B.A.P. form.
...
Only if required. In order to support various potential forms of supplied ROM.
2018-05-09 22:03:59 -04:00
c3a2f7717b
Makes attempt to implement support for the Pravetz 8D + 8DOS.
...
i.e. the Disk II wired up to the Oric, with some ROM swaps.
2018-05-08 22:05:43 -04:00
f65c65569a
Makes disk head position explicitly something with sub-integral precision.
...
Also as a drive-by fix, corrects accidental assumption of 10 sectors for all MFMSectorDump descendants.
2018-05-06 23:17:36 -04:00
aacf26f05d
Removed logged comment.
2018-04-30 22:03:09 -04:00
10c0e687f5
Attempts to introduce sleeping for the Disk II.
2018-04-29 17:51:10 -04:00
41075356e2
Makes a first attempt at NIB support.
2018-04-26 22:49:07 -04:00
d59db504a3
Adjusted stepper logic; some disks load now.
2018-04-25 21:59:18 -04:00
4c6dc597f4
Converts Time::get into a template, introduces a via-a-double fallback for the timed event loop.
2018-04-25 19:54:39 -04:00
Thomas Harte