2959 Commits

Author	SHA1	Message	Date
Thomas Harte	0b11fc259b	Add Archimedes-specific target class.	2024-05-13 21:42:38 -04:00
Thomas Harte	18ffb9294f	Add full cursor automation.	2024-05-12 22:16:29 -04:00
Thomas Harte	02ee3a7804	Turf out old debugging cruft.	2024-05-06 20:36:00 -04:00
Thomas Harte	bdf1dff976	Update version number.	2024-05-04 21:16:43 -04:00
Thomas Harte	7c9383cd6b	Update version number.	2024-04-20 14:45:21 -04:00
Thomas Harte	07984a2f8b	Resolve various warnings.	2024-04-17 22:15:05 -04:00
Thomas Harte	c807c75412	Revert version change.	2024-04-17 21:25:12 -04:00
Thomas Harte	f6feaddfe6	Add macOS route to starting empty Archimedes.	2024-04-17 20:44:45 -04:00
Thomas Harte	6ac6e48b95	Attempt audio output.	2024-04-13 21:54:50 -04:00
Thomas Harte	dd24f5f4f3	Don't latch video addresses until almost the last minute.	2024-04-09 20:56:10 -04:00
Thomas Harte	169298af42	Plumb through disk insertion. ... Surprisingly: some things now load.	2024-04-08 21:15:40 -04:00
Thomas Harte	d2b077c573	Start wiring in a floppy controller.	2024-04-07 21:22:35 -04:00
Thomas Harte	7d8a364658	Reimplement LDM and STM.	2024-04-04 21:59:18 -04:00
Thomas Harte	8a6bf84cff	Keyboard: log more, ignore unrecognised commands.	2024-03-29 20:54:07 -04:00
Thomas Harte	0ddbc67b1f	Switch to default CMOS RAM obtained from RISC OS itself.	2024-03-28 21:23:49 -04:00
Thomas Harte	bb339d619f	Eliminate trace test; I don't think I'm going to work it through.	2024-03-28 14:23:00 -04:00
Thomas Harte	2ed11877e8	Determine a couple of further exclusions.	2024-03-28 14:11:41 -04:00
Thomas Harte	ea6b83815b	Add a further category of exclusions.	2024-03-28 14:01:37 -04:00
Thomas Harte	740b0e35d5	Completely bypass ignored tests.	2024-03-28 11:28:37 -04:00
Thomas Harte	4fcb85d132	Cleave off most remaining reasons for failure.	2024-03-28 10:32:27 -04:00
Thomas Harte	c04c708a9d	Trade some depth for breadth.	2024-03-27 22:37:10 -04:00
Thomas Harte	f4cf1e5313	Attempt to cleave by broad reason.	2024-03-27 22:36:37 -04:00
Thomas Harte	3549488b7a	Add round-trip test for status flags.	2024-03-24 22:18:16 -04:00
Thomas Harte	5ccb18225a	Provide key states to the keyboard.	2024-03-23 15:43:04 -04:00
Thomas Harte	9ea3e547ee	Fix IRQ/FIQ return addresses.	2024-03-22 21:42:34 -04:00
Thomas Harte	de7b7818f4	Add 4bpp output.	2024-03-22 10:18:25 -04:00
Thomas Harte	1341816791	Break apart, switching to delegates for interrupts.	2024-03-20 14:26:56 -04:00
Thomas Harte	2ad6bb099b	Begin foray into disassembly.	2024-03-19 11:34:10 -04:00
Thomas Harte	7b1f800387	Extend I2C state machine.	2024-03-17 21:55:19 -04:00
Thomas Harte	47e9279bd4	Add a target for I2C activity.	2024-03-16 15:00:23 -04:00
Thomas Harte	3a899ea4be	Add test coverage for STM descending, proving nothing.	2024-03-15 14:55:17 -04:00
Thomas Harte	e7457461ba	Reduce magic constants.	2024-03-11 14:49:03 -04:00
Thomas Harte	ca779bc841	Expand test set.	2024-03-11 14:48:18 -04:00
Thomas Harte	db49146efe	Figure out what's going on with TEQ.	2024-03-11 09:51:09 -04:00
Thomas Harte	830d70d3aa	Trust tests on immediate-opcode ROR 0; limit shift by register.	2024-03-10 23:38:31 -04:00
Thomas Harte	336292bc49	Further correct R15 as a destination.	2024-03-10 22:56:02 -04:00
Thomas Harte	bd62228cc6	The test set doesn't seem to do word rotation.	2024-03-10 22:40:37 -04:00
Thomas Harte	ccdd340c9a	Reads also may or may not be aligned. *sigh*	2024-03-10 22:34:56 -04:00
Thomas Harte	0b42f5fb30	Make further test-set allowances.	2024-03-10 22:29:40 -04:00
Thomas Harte	21278d028c	Correct unaligned accesses.	2024-03-10 21:56:19 -04:00
Thomas Harte	fbc273f114	Add invented model for tests.	2024-03-10 21:45:56 -04:00
Thomas Harte	06a5df029d	Summarise failures.	2024-03-10 16:56:39 -04:00
Thomas Harte	e17700b495	Permit digression for 03110002, temporarily.	2024-03-10 14:47:02 -04:00
Thomas Harte	655b1e516c	Test PSR and PC.	2024-03-10 14:14:18 -04:00
Thomas Harte	4e7a63f792	Do a de minimis checking of memory accesses.	2024-03-09 15:18:35 -05:00
Thomas Harte	a2896b9bd0	Test register values.	2024-03-09 15:11:12 -05:00
Thomas Harte	d6f882a8bb	Integrate PC and PSR, guarantee invisible register values.	2024-03-09 14:59:44 -05:00
Thomas Harte	08f50f3eff	Box in flags.	2024-03-08 23:01:29 -05:00
Thomas Harte	47f7340dfc	Start hacking in some ARM tests.	2024-03-08 22:54:42 -05:00
Thomas Harte	9406a97141	Add some register switch tests.	2024-03-08 11:34:10 -05:00