313 Commits

Author	SHA1	Message	Date
Thomas Harte	509d011fbe	Implemented JP, my first Z80 operation.	2017-05-17 22:31:41 -04:00
Thomas Harte	17ffd604bf	Made an attempt to get the Z80 at least as far as rejecting an opcode.	2017-05-17 21:45:23 -04:00
Thomas Harte	1378ab7278	Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access.	2017-05-17 07:36:06 -04:00
Thomas Harte	87a021ec2d	Made further attempt to get as fas as having the Z80 attempt to do something.	2017-05-16 22:19:40 -04:00
Thomas Harte	7190f927b7	Factored out the stuff that both all-RAM processors would share, rather than duplicating it.	2017-05-16 21:28:17 -04:00
Thomas Harte	d559d8b901	Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.	2017-05-16 21:19:17 -04:00
Thomas Harte	50bb4f0142	There's finally a loop in here, at least.	2017-05-15 22:25:52 -04:00
Thomas Harte	7da51602d5	Moved flush, added run_for_cycles, which does nothing right now.	2017-05-15 07:59:21 -04:00
Thomas Harte	5152517887	Added the boilerplate stuff necessary to query registers.	2017-05-15 07:55:53 -04:00
Thomas Harte	eb8a2de5d6	Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.	2017-05-15 07:38:59 -04:00
Thomas Harte	f2a1a906ff	Adapted what negligible amount there is of the z80 as per the new CPU namespace.	2017-05-14 22:15:16 -04:00
Thomas Harte	0808e9b6fb	Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.	2017-05-14 22:08:15 -04:00
Thomas Harte	b81a2cc273	First tentative steps towards adding a Z80 implementation.	2017-05-14 17:46:41 -04:00