Thomas Harte
73e1c8c780
Corrects now-unimplemented ADD/SUB.
2019-04-03 19:43:54 -04:00
Thomas Harte
2c5ff9ada0
Switches to running the real TOS, at least temporarily, and enables better testing.
2019-03-31 22:27:57 -04:00
Thomas Harte
b0b2798f39
Updates to track Swift.
2019-03-27 21:25:51 -04:00
Thomas Harte
47359dc8f1
Adds tests for MOVE.l (An), Dn, and thereby correct their implementation.
2019-03-23 21:41:47 -04:00
Thomas Harte
d7c3d4ce52
Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof.
2019-03-22 23:27:48 -04:00
Thomas Harte
87420881c8
Extends to a failing test.
2019-03-21 23:32:03 -04:00
Thomas Harte
fdc598f2e1
Starts MOVE tests; in pursuit of which talks the 68000 into obeying run lengths.
2019-03-21 22:30:41 -04:00
Thomas Harte
0d7bbdad54
Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix.
2019-03-17 21:57:00 -04:00
Thomas Harte
388d808536
Switches to providing UDS and LDS implicitly via address.
...
Also makes sure that the difference between a non-data cycle that starts without the address strobe active and one that starts with it active can be discerned.
2019-03-16 17:54:58 -04:00
Thomas Harte
720aba3f2d
Adds an implementation of SBCD and slightly neatens syntax for building programs.
2019-03-14 21:22:02 -04:00
Thomas Harte
f9101de956
This might very well be the 68000's first real gasp: performing an ABCD.
2019-03-14 19:32:15 -04:00
Thomas Harte
9e8928aad9
Implements as much as I currently care about of the Atari ST memory map.
2019-03-11 22:47:37 -04:00
Thomas Harte
89c71f9119
Introduces EmuTOS, and starts constructing test cases around it.
2019-03-10 18:40:12 -04:00
Thomas Harte
a4f6db6719
Removes ArrayBuilderTests as the ArrayBuilder is long gone. Disables TIA tests for now.
2019-03-10 18:07:23 -04:00
Thomas Harte
6a93d2d006
Corrects some minor spaces-instead-of-tabs errors.
2019-01-24 22:59:03 -05:00
Thomas Harte
ee89be6730
Removes many stray spaces.
2018-11-23 22:32:32 -05:00
Thomas Harte
a8645f80bf
Introduces 'non-exclusive' emulator-space keyboards.
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i.e. sets of keys that don't amount to an entire keyboard in the modern sense. Experimentally used by the Master System for its reset key.
2018-10-24 21:59:30 -04:00
Thomas Harte
c07f9fed99
Corrects test and implementation to pass the exhaustive VDP interrupt prediction test.
2018-10-21 18:42:49 -04:00
Thomas Harte
616777517d
Makes the failing test more communicative, in the hope of more easily debugging errors.
2018-10-21 14:35:44 -04:00
Thomas Harte
b3f1677da5
Introduces new failing test for rational continuous interrupt prediction.
2018-10-21 13:59:14 -04:00
Thomas Harte
725b364bbc
Improves testing; now tests for time to the first interrupt.
2018-10-20 18:25:55 -04:00
Thomas Harte
acdc84e08c
Improves test slightly, and fixes line interrupt reload value setting.
2018-10-09 22:14:35 -04:00
Thomas Harte
c128ddb549
Introduces a first unit test for line interrupts and corrects backup behaviour.
2018-10-09 21:49:21 -04:00
Thomas Harte
fc84ae611e
Resolves various instances of spaces in place of tabs.
2018-09-09 20:33:56 -04:00
Thomas Harte
ddf45a0010
Ensures NMI and RST reset D on 65C02s.
2018-08-14 19:49:14 -04:00
Thomas Harte
261fb3d4f8
Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing.
...
This gets Klaus Dorman's test to pass.
2018-08-10 22:42:35 -04:00
Thomas Harte
b63e0cff72
Improves has-completed test.
2018-08-10 22:27:01 -04:00
Thomas Harte
5d6e479338
Implements RMB and SMB, and fixes SBC (zero).
2018-08-10 22:13:51 -04:00
Thomas Harte
90094529a5
Implements TSB and TRB, and adds the extra BIT instructions.
2018-08-10 22:04:45 -04:00
Thomas Harte
aed4c0539e
Implements STZ.
2018-08-10 21:17:02 -04:00
Thomas Harte
95164b79c9
Attempted implementation of (zp) addressing mode.
2018-08-09 21:51:14 -04:00
Thomas Harte
bb680b40d8
Implements the 65C02's JMPs.
2018-08-08 22:26:57 -04:00
Thomas Harte
e3f6da6994
Implements the 65C02 NOPs.
2018-08-08 20:00:14 -04:00
Thomas Harte
32338bea4d
Implements BRA.
2018-08-06 22:37:30 -04:00
Thomas Harte
1a44ef0469
Introduces Klaus Dorman's 65C02 tests. All failing.
2018-08-06 21:48:43 -04:00
Thomas Harte
ebce9a2e51
Fixes test target.
2018-08-06 21:15:13 -04:00
Thomas Harte
abca38a548
Makes an initial removal of PCMPatchedTrack. Farewell, old friend.
2018-07-01 22:49:57 -04:00
Thomas Harte
853261364e
Generalised CRC generation and created specific subclasses for the CCITT CRC16 and CRC32.
2018-05-23 22:21:57 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
05e31d7594
Mutates testComplicatedTrackSeek into an actual test.
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Which frustratingly passes.
2018-05-01 19:52:12 -04:00
Thomas Harte
f4097290c2
Made various corrections following a quick for-loop constness audit.
2018-04-30 22:23:57 -04:00
Thomas Harte
b32538f3c8
Adds an additional test.
2018-04-30 22:05:44 -04:00
Thomas Harte
e7618bb32e
Corrects types (/chickens out).
2018-04-30 22:04:05 -04:00
Thomas Harte
e599e65087
Switches to use of the TargetList typedef wherever possible.
2018-04-14 19:46:38 -04:00
Thomas Harte
389979923e
Performs update to and satisfaction of Xcode 9.3's preferred warnings.
2018-03-30 10:25:01 -04:00
Thomas Harte
f0f9d5a6af
Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
2018-03-08 20:30:22 -05:00
Thomas Harte
fdef914137
Corrects test target regression.
2018-03-06 18:32:21 -05:00
Thomas Harte
66faed4008
Gives MachineForTargets complete responsibility for initial machine state.
2018-01-25 18:28:19 -05:00
Thomas Harte
21efb32b6f
Integrates the static and nascent dynamic analyser namespaces.
2018-01-24 21:48:44 -05:00
Thomas Harte
ed564cb810
Implements the main four cartridge banking schemes.
...
Slightly proof of concept for now.
2018-01-04 22:18:18 -05:00
Thomas Harte
c8367a017f
Cleans up test and makes attempt to factor in cartridge type popularity.
2018-01-01 21:21:05 -05:00
Thomas Harte
344a12566b
Tweaks a couple of expected cartridge types.
2018-01-01 20:14:56 -05:00
Thomas Harte
c07113ea95
Ensures no illegal accesses while testing MSX ROM type detection.
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Specifically: the static analyser doesn't even correctly identify everything that is an MSX ROM yet, let alone then properly determine type.
2018-01-01 17:38:26 -05:00
Thomas Harte
bc2879c412
Corrects the MSX ROM unit test.
...
I.e. the test is correct now, for those SHAs I could find. The static analyser is still wrong just slightly less than half the time.
2018-01-01 17:35:13 -05:00
Thomas Harte
db25b4554b
Introduces failing tests of the MSX static analyser.
2018-01-01 16:38:26 -05:00
Thomas Harte
05b95ea2e0
Corrects Xcode tests.
2018-01-01 16:04:13 -05:00
Thomas Harte
6e1d69581c
Eliminates a variety of end-of-line spaces.
2017-11-07 22:54:22 -05:00
Thomas Harte
f95515ae81
Eliminates a large number of instance of end-of-line tabs.
2017-11-07 22:51:06 -05:00
Thomas Harte
064f1dfdbc
Removes usages of deprecated initialiser.
2017-10-05 18:10:47 -04:00
Thomas Harte
ff24e1de31
Corrects 6522 bridge per has-a-not-is-a template switch.
2017-09-04 21:56:21 -04:00
Thomas Harte
7af3de010e
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
761afad118
Corrected timestamp return, and its testing by the 6502 timing tests.
2017-07-27 21:19:16 -04:00
Thomas Harte
37950143fc
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
Thomas Harte
9257a3f6d7
Added test for 16-bit arithmetic, and fixed implementation.
2017-07-26 19:04:52 -04:00
Thomas Harte
728143247d
Added a test for RLD and RRD. Which already passes.
2017-07-26 18:56:35 -04:00
Thomas Harte
6ec4e4e3d7
Merge branch 'master' into Memptr
2017-07-25 23:01:34 -04:00
Thomas Harte
37ccb9d3b6
Fixed 6502 timing tests.
2017-07-25 23:00:39 -04:00
Thomas Harte
3c254360ba
Completed fixture of the 6502 BCD test.
2017-07-25 22:55:45 -04:00
Thomas Harte
3ca51bedc6
Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses.
2017-07-25 22:48:44 -04:00
Thomas Harte
36076b7ea5
Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams.
2017-07-25 22:38:26 -04:00
Thomas Harte
df4732be2e
Corrected test.
2017-07-24 22:33:49 -04:00
Thomas Harte
9435c1e12a
The 1540 is now a ClockReceiver.
2017-07-24 22:32:41 -04:00
Thomas Harte
2912d7055b
The 6532 is now a ClockReceiver.
2017-07-24 21:57:24 -04:00
Thomas Harte
13f7aa4063
The TIA is now a ClockReceiver.
2017-07-24 21:48:34 -04:00
Thomas Harte
b3ae920746
Converted the DPLL and disk controller classes to be ClockReceivers.
2017-07-24 21:04:47 -04:00
Thomas Harte
e6578defcd
It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.
2017-07-23 22:22:50 -04:00
Thomas Harte
ace8e30818
Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
2017-07-23 22:21:39 -04:00
Thomas Harte
b0c2325adc
Corrected run call, and accepted that jam handling is gone forever.
2017-07-22 22:21:26 -04:00
Thomas Harte
4ea835e50b
Added test for EX (SP), rp, which passes.
2017-07-22 17:17:32 -04:00
Thomas Harte
6437c43147
Added CPI and CPD tests: at last two that pass without requiring implementation changes!
2017-07-22 12:38:18 -04:00
Thomas Harte
5928a24803
Transcribed missing tests as TODOs.
2017-07-22 11:44:17 -04:00
Thomas Harte
20a6bcc676
Added tests for the various LD (nn), rr instructions and corrected implementation to pass.
2017-07-22 11:39:13 -04:00
Thomas Harte
eaf313b0f6
Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
2017-07-22 11:20:21 -04:00
Thomas Harte
d51b66c204
Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
2017-07-21 23:01:35 -04:00
Thomas Harte
660f0e4c40
Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.
2017-07-21 22:52:25 -04:00
Thomas Harte
7b5f93510b
Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.
2017-07-16 20:55:57 -04:00
Thomas Harte
8ddd686049
Removed redundant variable.
2017-07-16 19:04:03 -04:00
Thomas Harte
2fb0aea990
Updated the C1540 test vessel to the new world.
2017-07-16 17:00:39 -04:00
Thomas Harte
95a6b0f85c
Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
2017-06-22 21:09:26 -04:00
Thomas Harte
0e0ce379b4
Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
2017-06-21 20:38:08 -04:00
Thomas Harte
36e8a11505
Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
2017-06-21 20:32:08 -04:00
Thomas Harte
108da64562
Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
2017-06-20 22:25:00 -04:00
Thomas Harte
184b371649
Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
2017-06-20 21:48:50 -04:00
Thomas Harte
27ac342928
Corrected conditional call timing, and its test.
2017-06-20 20:57:23 -04:00
Thomas Harte
6752f165db
Added failing tests for both kinds of CALL.
2017-06-19 22:03:29 -04:00
Thomas Harte
e05076b258
Added tests for everything except CALL. All passing.
2017-06-19 22:00:04 -04:00
Thomas Harte
fadbfdf801
Added DJNZ test.
2017-06-19 21:31:56 -04:00
Thomas Harte
cb277b8d1e
Added JP and JR tests.
2017-06-19 21:27:23 -04:00
Thomas Harte
234f14dbbe
Tests were at fault; all passing now.
2017-06-19 21:14:40 -04:00
