Thomas Harte
|
4abd62e62b
|
Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
|
2017-07-27 22:05:29 -04:00 |
|
Thomas Harte
|
a1e9a54765
|
Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
|
2017-07-25 20:09:13 -04:00 |
|
Thomas Harte
|
8a2bdb8d22
|
Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.
|
2017-07-24 21:19:05 -04:00 |
|
Thomas Harte
|
8755824c64
|
Added some documentation.
|
2017-07-22 17:25:53 -04:00 |
|
Thomas Harte
|
64865b3f41
|
Signedness fixes.
|
2017-07-21 21:23:34 -04:00 |
|
Thomas Harte
|
53f0e1896b
|
Made delay_time_ unsigned for safe comparison.
|
2017-07-21 21:21:23 -04:00 |
|
Thomas Harte
|
e01f3f06c8
|
Completed curly bracket movement.
|
2017-03-26 14:34:47 -04:00 |
|
Thomas Harte
|
eca3995481
|
Added a CRC check for read address, ensured CRC, lost data and record not found are initially reset.
|
2017-01-01 21:00:25 -05:00 |
|
Thomas Harte
|
044c920a5b
|
Made it more explicit that there are no unhandled cases.
|
2017-01-01 20:56:52 -05:00 |
|
Thomas Harte
|
0df9ce5a76
|
Made an attempt at read address. So superficially that leaves only the force interrupts.
|
2017-01-01 20:55:09 -05:00 |
|
Thomas Harte
|
f94f34f053
|
Made an attempt at read track. Which means process_input_bit can't just swallow syncs any more; it now reports them as tokens of type ::Sync.
|
2017-01-01 20:39:19 -05:00 |
|
Thomas Harte
|
c994fa39f6
|
Ensured spin-up doesn't occur if there's no motor line.
|
2016-12-31 16:18:30 -05:00 |
|
Thomas Harte
|
1ea4f0d79d
|
Made an attempt to implement 'write track' and ensure that 'write sector' can't end without announcing that it has ended writing.
|
2016-12-31 16:01:44 -05:00 |
|
Thomas Harte
|
8eb21c6702
|
The "MFM...Byte"s aren't MFM-specific, they're relevant to both FM and MFM encoding. So renamed them. Also slimmed syntax within MFM.cpp mostly where emigration from the Acorn disk analyser had left a residue of lengthy namespace specification.
|
2016-12-31 15:25:11 -05:00 |
|
Thomas Harte
|
a8bc9d830e
|
Removed leftover very temporary debugging aid.
|
2016-12-28 23:03:05 -05:00 |
|
Thomas Harte
|
e4000bd060
|
Added some even more verbose logging; slightly simplified write loop logic, and decided it's definitely write_byte that's responsible for CRC generator feeding.
|
2016-12-28 21:24:19 -05:00 |
|
Thomas Harte
|
4adcb46665
|
Fixed FM-mode CRC generation.
|
2016-12-28 19:51:27 -05:00 |
|
Thomas Harte
|
1277a67f9a
|
Introduced data_mode_ to replace is_reading_data_, representing that there are now three possible modes. When writing, any input from the read head won't affect the CRC generator.
|
2016-12-28 19:26:21 -05:00 |
|
Thomas Harte
|
7a627b782d
|
Reintroduced writing of MFM sync marks when writing a sector.
|
2016-12-28 18:48:50 -05:00 |
|
Thomas Harte
|
a568172758
|
Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs.
|
2016-12-28 18:29:37 -05:00 |
|
Thomas Harte
|
9c0f622a2e
|
Started working CRC checking into the 1770. Discovered immediately that my generated CRC does not match that built into the Oric disk images. So mine is pretty-much certainly wrong. An opportunity for learning!
|
2016-12-26 16:46:26 -05:00 |
|
Thomas Harte
|
0490a47058
|
Worked on the all-around framework for decoding sectors back from tracks when closing down a file. Hit the wall that the parser is more observant of CRCs than the WD. No, really. So I guess I have to stop avoiding that whole issue.
|
2016-12-26 14:24:33 -05:00 |
|
Thomas Harte
|
83c433c142
|
Deviated from the data sheet, which seems likely to be correct. Hence removed a whole load of the temporary logging.
|
2016-12-26 12:48:49 -05:00 |
|
Thomas Harte
|
742c5df367
|
With lots of logging arising temporarily, fixed bug whereby conversion to a patched track would lead to holding a track with a distinct measure of time, leading to improperly-placed patches.
|
2016-12-25 22:00:39 -05:00 |
|
Thomas Harte
|
acc35885cd
|
Attempted to reduce track invalidations.
|
2016-12-25 20:38:25 -05:00 |
|
Thomas Harte
|
c0a1264ab0
|
Slightly improved legibility.
|
2016-12-25 20:19:47 -05:00 |
|
Thomas Harte
|
e2b829f68e
|
Made an attempt to write the proper address mark.
|
2016-12-25 20:15:07 -05:00 |
|
Thomas Harte
|
beaa868079
|
Factored the MFM parser out into encodings.
|
2016-12-25 20:00:57 -05:00 |
|
Thomas Harte
|
74e98fd097
|
Made an attempt to write actual data (albeit that CRC calculation is still missing).
|
2016-12-25 19:18:45 -05:00 |
|
Thomas Harte
|
98be6ede45
|
Shuffled a little to reduce risk of overflow, ensured writing is a loop, still seem to be writing too quickly for some reason.
|
2016-12-25 16:13:05 -05:00 |
|
Thomas Harte
|
d2ad2c756e
|
Added enough shovelling to write rubbish for an entire sector.
|
2016-12-25 15:46:49 -05:00 |
|
Thomas Harte
|
aceb7e3b6b
|
Started implementing write sector on the 1770, immediately deciding it would be useful to have a callback for end-of-queued-data-written from disk controller. So had a go at implementing that, naively. More investigation required.
|
2016-12-25 12:31:38 -05:00 |
|
Thomas Harte
|
901f19f89c
|
Added enough stuff that SSDs attached to a 1770 will now reach the entry point for writing.
|
2016-12-25 09:46:12 -05:00 |
|
Thomas Harte
|
c304db0f5a
|
Deintegrated the busy flag and the interrupt request line, as the latter is reset by status reads. Which also means I can start reporting the WD INTRQ line status directly from the Microdisc. That appears to be correct, rather than honouring the Microdisc IRQ select there.
|
2016-12-06 21:16:29 -05:00 |
|
Thomas Harte
|
81ee834530
|
As well as a bunch of logging, reinstated rotation position preservation across tracks.
|
2016-12-02 18:36:47 -05:00 |
|
Thomas Harte
|
93c573bfa9
|
Implemented missing status bits (other than the index hole), and a head loading delay for the Microdisc.
|
2016-12-01 21:13:16 -05:00 |
|
Thomas Harte
|
0a0775c3bd
|
Removed earlier hacky solution.
|
2016-12-01 20:16:11 -05:00 |
|
Thomas Harte
|
442986ee2c
|
Introduced a head loading path for 1793 machines.
|
2016-12-01 20:12:22 -05:00 |
|
Thomas Harte
|
82899f2f47
|
Ensured flag setting is atomic, removed duplication of interrupt request versus busy, found better names for the personality testers, unified delegate protocol.
|
2016-12-01 07:41:52 -05:00 |
|
Thomas Harte
|
b31fd11470
|
Fixed reporting of data request line, initial status values.
|
2016-11-30 22:39:55 -05:00 |
|
Thomas Harte
|
2222cb65d6
|
Split the status up into flags, assembled into a register upon demand. Attempted to implement some of the differences between the 1770/1772 and 1773/1793. Albeit with a motor fix still in place.
|
2016-11-30 22:26:02 -05:00 |
|
Thomas Harte
|
84cb07613d
|
Checked some documentation more thoroughly; the 1793 has quite different spin-up (/head load) semantics. So it's another distinct personality. Grrr.
|
2016-11-27 20:39:08 -08:00 |
|
Thomas Harte
|
02ba1f220f
|
The '72 seems to be a '70 with altered timing. So worth differentiating.
|
2016-11-27 21:06:17 +08:00 |
|
Thomas Harte
|
2c01f9dbed
|
Added meaningful TODOs.
|
2016-11-27 08:42:39 +08:00 |
|
Thomas Harte
|
2f459690d4
|
It would appear the 1770 and 1773 actually differ in relation to the (non-sensical) ability not to spin-up for a Type 2, and whether a side compare can occur. So the WD1770 class now requires a personality to be specified. Which it singly fails to honour.
|
2016-11-26 23:29:30 +08:00 |
|
Thomas Harte
|
d8ecc52de8
|
Temporarily disabled spin-down as harmful to the status register if following anything other than a Type 1 command.
|
2016-11-26 22:27:20 +08:00 |
|
Thomas Harte
|
b9677c9927
|
Consolidated interrupt request setting.
|
2016-11-26 09:41:53 +08:00 |
|
Thomas Harte
|
d5f9e0aa3b
|
Ensured there's no such thing as a zero-cycle operation, even if i don't yet know exactly what I should be doing.
|
2016-11-25 21:24:25 +08:00 |
|
Thomas Harte
|
4af678d2ed
|
Gave the Microdisc a clock signal, added just enough of force interrupt to avoid a spurious belief that a type 3 command has started.
|
2016-11-25 20:51:39 +08:00 |
|
Thomas Harte
|
d4a1961378
|
Added getters for the IRQ and DRQ lines plus a delegate to receive changes; adjusted code so that the two lines signal.
|
2016-11-21 13:21:49 +08:00 |
|