Thomas Harte
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1aba1db62c
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Corrects test.
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2019-10-27 21:30:58 -04:00 |
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Thomas Harte
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0fc191c87d
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Switched a few static_cast to constructor syntax.
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2019-10-27 14:21:22 -04:00 |
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Thomas Harte
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dc4a0e4e3b
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Video only ever reads from RAM, so it can be const *.
(it can also be *const, since I set it only once)
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2019-10-27 14:09:38 -04:00 |
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Thomas Harte
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3794d94b68
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Adds a sanity check on alignment.
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2019-10-27 14:09:02 -04:00 |
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Thomas Harte
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0082dc4411
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Improves logging.
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2019-10-27 00:02:55 -04:00 |
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Thomas Harte
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22754683f8
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Ensures timer divisor values don't go out of range, adds timer interrupts.
I suspect further timer issues remain.
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2019-10-26 23:20:13 -04:00 |
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Thomas Harte
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909685d87d
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A drive with no disk is now happy to spin its motor.
It'll continue to produce index-hole events, which might not be accurate for 5.25" drives. Research to do.
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2019-10-26 22:57:05 -04:00 |
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Thomas Harte
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55710ea00e
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Switches the presumption to requiring NDEBUG to avoid forced inlines.
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2019-10-26 22:43:25 -04:00 |
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Thomas Harte
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36a9a5288b
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Adds drives to the FDC.
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2019-10-26 22:39:11 -04:00 |
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Thomas Harte
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e89be6249d
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Adds a logging prefix.
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2019-10-26 22:38:56 -04:00 |
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Thomas Harte
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ac39fd0235
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Starts work on the DMA controller.
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2019-10-26 21:33:57 -04:00 |
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Thomas Harte
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ecc0cea5a1
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Added a potential branch for the newer TOS memory map.
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2019-10-26 16:52:06 -04:00 |
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Thomas Harte
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eae11cbf17
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Adds a dummy response for mouse interrogation.
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2019-10-26 16:14:24 -04:00 |
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Thomas Harte
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e96386f572
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Takes another stab at MFP interrupt management.
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2019-10-26 15:55:19 -04:00 |
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Thomas Harte
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a8d481a764
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Writes to the pending register appear to be able to clear interrupts too.
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2019-10-25 22:46:30 -04:00 |
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Thomas Harte
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2207638287
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Adds hsync and vsync interrupts.
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2019-10-25 22:42:13 -04:00 |
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Thomas Harte
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872897029e
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Attempts a complete wiring of 68901 interrupts.
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2019-10-25 22:36:01 -04:00 |
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Thomas Harte
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51b4b5551d
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Actually, I think the 6850 is active low for interrupts.
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2019-10-24 22:37:53 -04:00 |
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Thomas Harte
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7a2de47f58
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Corrects interrupt mask generation.
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2019-10-24 22:37:32 -04:00 |
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Thomas Harte
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f2f98ed60c
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Attempts some part of interrupt decision making.
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2019-10-24 22:33:42 -04:00 |
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Thomas Harte
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77f14fa638
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Starts trying to make sense of interrupts.
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2019-10-23 23:09:49 -04:00 |
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Thomas Harte
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f09a240e6c
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Gives myself more trace details.
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2019-10-21 23:20:03 -04:00 |
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Thomas Harte
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092a61f93e
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Does a better job of having just 512kb.
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2019-10-21 23:10:30 -04:00 |
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Thomas Harte
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e30ba58e0d
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Attempts to wire ACIA interrupt signals into the MFP.
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2019-10-21 23:02:30 -04:00 |
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Thomas Harte
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7cb82fccc0
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Attempts properly to maintain interrupt flag; adds delegate.
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2019-10-21 22:40:38 -04:00 |
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Thomas Harte
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ed9a5b0430
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Adds receipt interrupt.
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2019-10-21 21:27:57 -04:00 |
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Thomas Harte
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8f59a73425
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Corrects incoming data capture.
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2019-10-21 20:18:52 -04:00 |
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Thomas Harte
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91223b9ec8
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Sets default level to high.
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2019-10-21 20:18:33 -04:00 |
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Thomas Harte
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83f5f0e2ad
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Begins trying to receive ACIA data.
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2019-10-21 20:10:19 -04:00 |
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Thomas Harte
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cf37e9f5de
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Remove source control markers.
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2019-10-20 23:40:51 -04:00 |
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Thomas Harte
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e4f7ead894
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Merge branch 'AtariST' of github.com:TomHarte/CLK into AtariST
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2019-10-20 23:40:01 -04:00 |
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Thomas Harte
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4134463094
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The ACIA now receives bits.
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2019-10-20 23:34:30 -04:00 |
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Thomas Harte
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83d73fb088
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The keyboard now responds to a reset on its serial line.
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2019-10-20 23:13:44 -04:00 |
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Thomas Harte
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75c3e2dacd
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Adds basic, incomplete dispatcher for the intelligent keyboard.
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2019-10-20 23:07:19 -04:00 |
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Thomas Harte
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cf07982a9b
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Ensures good serial line and ACIA behaviour.
Next stop: having the intelligent keyboard react.
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2019-10-20 22:10:05 -04:00 |
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Thomas Harte
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313aaa8f95
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Silences temporarily.
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2019-10-20 20:38:56 -04:00 |
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Thomas Harte
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2e86dada1d
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Ensures updates even when the event queue is empty.
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2019-10-20 20:38:56 -04:00 |
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Thomas Harte
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696af5c3a6
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Starts to transfer serial line decoding logic into the line itself.
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2019-10-20 20:38:56 -04:00 |
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Thomas Harte
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f08b38d0ae
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Silences, temporarily.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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9a8352282d
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Mostly but not quite fixes serial work.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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3d03cce6b1
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Starts working on the GPIP functionality block.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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34075a7674
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Attempts to tie an intelligent keyboard to the other end of its serial line.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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f79c87659f
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Corrects documentation error.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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c10b64e1c0
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Adds a received_data_ register, that presently can never fill.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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5d5fe52144
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Corrects transmission logic — exactly hitting write_data_time_remaining now works properly.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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d461331fd2
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Ensures remaining_delays_ is set properly after [reset/flush]_writing.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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ff62eb6dce
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The ACIA actually has two clocks, though on an ST they're both 500,000 Hz.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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374439693e
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Ensures serial lines know their writer's clock rate.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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c4ef33b23f
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JustInTimeActors can now specify a clock divider.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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a7ed357569
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Attempts to implement transmission interrupts and ClockingHint::Source.
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2019-10-20 20:38:55 -04:00 |
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