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13,175 Commits 3 Branches 145 Tags
5dc00a209239562b95a836222f48602fcfaf7996
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1352 Commits

Author SHA1 Message Date
Thomas Harte 5dc00a2092 Update #undef list. 2025-10-24 12:00:22 -04:00
Thomas Harte b20d489bf0 Remove SHA/SHX/etc. 2025-10-24 11:58:55 -04:00
Thomas Harte df39870587 Factor out index decision. 2025-10-24 11:53:55 -04:00
Thomas Harte f742eab4be Reduce to a generic case. 2025-10-23 21:54:50 -04:00
Thomas Harte e9c8c61dcf Reformulate to be slightly more conditional, but substantially deduplicate code. 2025-10-23 21:52:31 -04:00
Thomas Harte e5f09002e9 Extract bit operators. 2025-10-23 20:47:55 -04:00
Thomas Harte d42f005e17 Improve consistency. 2025-10-23 20:43:15 -04:00
Thomas Harte 24e060abee Elide ADC logic. 2025-10-23 19:54:07 -04:00
Thomas Harte 8b6d763442 Reduce duplication within ARR. 2025-10-23 19:42:36 -04:00
Thomas Harte e239745f63 Fix typo. 2025-10-23 19:35:40 -04:00
Thomas Harte cfef2b4e19 Eliminate 16-bit arithmetic from SBX. 2025-10-23 19:32:50 -04:00
Thomas Harte cf93c39881 Pull out overflow logic, remove 16-bit arithmetic from ADC. 2025-10-23 18:23:09 -04:00
Thomas Harte 5d223bce4c Pull out and simplify compare. 2025-10-23 17:47:15 -04:00
Thomas Harte b454ebc1c9 Extricate further operations. 2025-10-23 17:41:13 -04:00
Thomas Harte 7cf9910cae Pull ADC, SBC and some others out. 
This resolves the wacky control flow somewhat.
 2025-10-23 17:15:21 -04:00
Thomas Harte 79ab1d8cb1 Implement final SHA. 2025-10-23 13:42:23 -04:00
Thomas Harte 7cd20f5d12 Add all absolute-indexed oddities. 2025-10-23 13:39:03 -04:00
Thomas Harte 5396d751e1 Support SHX and a SHA. 2025-10-23 13:27:55 -04:00
Thomas Harte d23e715650 Decision: these five have weird addressing, so that counts as weird addressing modes. 2025-10-23 13:13:01 -04:00
Thomas Harte 0791bce338 Fix everything other than the oddball SHA/SHX/SHY/SHS. 2025-10-22 22:12:32 -04:00
Thomas Harte 2bcb74072a Add trqnsfers, correct a STA. 2025-10-22 21:20:11 -04:00
Thomas Harte c5f2f17f33 Further populate perform. 
First failing test is now 0x8a.
 2025-10-22 21:13:57 -04:00
Thomas Harte 62a8bf4261 Add missing RTS cycle. 2025-10-22 17:56:11 -04:00
Thomas Harte ebda18b44e Implement the two JMPs. 2025-10-22 17:52:55 -04:00
Thomas Harte a8f41b9017 Implement RTI and RTS. 2025-10-22 17:48:19 -04:00
Thomas Harte 410c19a7da Fix pull. 2025-10-22 17:43:08 -04:00
Thomas Harte a346e2e04b Transcribe bit logic. 2025-10-22 17:40:03 -04:00
Thomas Harte 2d114b6677 Implement JSR. 2025-10-22 17:37:01 -04:00
Thomas Harte 02e74ca1f4 Add absolute-indexed addressing. 2025-10-22 17:18:54 -04:00
Thomas Harte 69122cdec4 Swing at zero-indexed addressing. 2025-10-22 17:12:23 -04:00
Thomas Harte d730168631 Remove dead label. 2025-10-22 13:30:24 -04:00
Thomas Harte 2f210ebe3b Fix IndexedIndirect/IndirectIndexed confusion, proceed to test 0x14. 2025-10-22 13:29:45 -04:00
Thomas Harte 693b53baa2 Proceed through absolute addressing to test 0x10. 2025-10-22 13:05:46 -04:00
Thomas Harte 77554879a5 Add missing 0x?e group. 2025-10-22 13:00:36 -04:00
Thomas Harte 45363922b5 Adds rolls and shifts, and zero-page addressing. 2025-10-22 12:56:07 -04:00
Thomas Harte 0463c1ceda Reduce repetition. 2025-10-21 23:21:11 -04:00
Thomas Harte b35a55a658 Implement jamming. 2025-10-21 23:16:59 -04:00
Thomas Harte 4da68c9fa8 Implement IndirectIndexedRead. 2025-10-21 23:01:41 -04:00
Thomas Harte 72f133f31b Do enough work to verify BRK. 2025-10-21 22:07:35 -04:00
Thomas Harte af4a8f6d9c Add enough to attempt to run processor tests. 2025-10-21 21:30:42 -04:00
Thomas Harte b5899a2e42 Implement simplest operations. 2025-10-21 17:33:36 -04:00
Thomas Harte 4ee8f8564e Catch unimplemented. 2025-10-21 13:40:23 -04:00
Thomas Harte ff08c03bc5 Coral into building. 2025-10-21 13:31:48 -04:00
Thomas Harte 95dd430b0d Shoehorn in an invocation. 2025-10-21 13:12:58 -04:00
Thomas Harte 20eb8b1442 Move RDY inline. 2025-10-21 12:59:16 -04:00
Thomas Harte 2d6a0b3ed0 Add a branch to nowhere. 2025-10-20 23:08:04 -04:00
Thomas Harte 80f0ce78e0 Eliminate unused enum. 2025-10-20 22:51:12 -04:00
Thomas Harte fde0e2434e Attempt to transcribe base 6502 instruction set. 2025-10-20 22:50:14 -04:00
Thomas Harte 2cdf6ac8f9 Add interrupt, RDY and instruction fetch logic. 2025-10-20 13:16:03 -04:00
Thomas Harte 309c58a93d Include in CI builds; start implementation. 2025-10-19 23:29:27 -04:00