1596 Commits

Author	SHA1	Message	Date
Thomas Harte	7015e46227	Put together enough of an interface to expect to see some pixels.	2025-09-24 22:08:04 -04:00
Thomas Harte	cce2607c80	Add file for SAA5050 logic.	2025-09-24 21:43:25 -04:00
Thomas Harte	068726e0ab	Add TODO.	2025-09-24 21:26:04 -04:00
Thomas Harte	89e86ad9bd	Delay publication of the refresh address.	2025-09-24 21:20:20 -04:00
Thomas Harte	174c8dafbf	Resolve potential out-of-phase line counter.	2025-09-24 17:26:40 -04:00
Thomas Harte	90a96293de	Implement interlace-dependent row addressing.	2025-09-24 17:20:04 -04:00
Thomas Harte	84877c4fec	Reenable the cursor; good enough for now.	2025-09-24 14:37:52 -04:00
Thomas Harte	a7cceb5fa9	Avoid circular state dependency.	2025-09-24 14:30:37 -04:00
Thomas Harte	ca6359a597	Reintroduce pixels, proving myself to be off-by-one.	2025-09-24 14:29:25 -04:00
Thomas Harte	b7c3667be1	Work out inadvertent discrepancies.	2025-09-24 14:11:06 -04:00
Thomas Harte	b6dea59db3	This tests lines, not rows.	2025-09-24 13:56:16 -04:00
Thomas Harte	aa51f13743	Reorder to avoid dependencies upon values that mutate.	2025-09-24 13:54:09 -04:00
Thomas Harte	f34ec03ff0	Attempt to fix off-by-one; adopt fixed pixel pattern.	2025-09-24 13:42:17 -04:00
Thomas Harte	1363be59b7	Formalise field size.	2025-09-24 11:17:47 -04:00
Thomas Harte	622c24ef24	This indicates a line, not a row.	2025-09-23 22:36:56 -04:00
Thomas Harte	539b0e49d4	Start in mode 7, reallow interlaced modes.	2025-09-23 14:45:32 -04:00
Thomas Harte	0c42976312	Add notes to self.	2025-09-23 14:42:16 -04:00
Thomas Harte	67e1773495	This flag covers rows, not lines.	2025-09-23 14:29:00 -04:00
Thomas Harte	a199b64aa0	Clarify naming, attempt better to conform to FPGA precedent.	2025-09-23 14:27:21 -04:00
Thomas Harte	0349931953	Shuffle declare order.	2025-09-22 13:21:48 -04:00
Thomas Harte	d612a385d2	Dig in further on types.	2025-09-22 13:20:10 -04:00
Thomas Harte	ed4f299d55	Start formalising types.	2025-09-22 13:09:30 -04:00
Thomas Harte	66bfb86d42	Introduce SizedCounter as start of CRTC reworking.	2025-09-22 12:46:39 -04:00
Thomas Harte	fb5ef200fb	Correct uPD7002 interrupt wiring.	2025-09-20 21:51:19 -04:00
Thomas Harte	719a090b34	Retain bit 2.	2025-09-20 20:06:28 -04:00
Thomas Harte	3af85da6e0	Adjust conversion bits in status.	2025-09-20 19:52:47 -04:00
Thomas Harte	8fd62aa525	Disable interrupt at start of conversion.	2025-09-20 19:49:16 -04:00
Thomas Harte	eef0ee8180	Support cursor to end of row.	2025-09-20 08:27:58 -04:00
Thomas Harte	ff0ba7d48b	Reduce logging again.	2025-09-19 22:59:58 -04:00
Thomas Harte	3916ba1a42	This intermittently succeeds. Doubling down on investigation.	2025-09-19 20:33:02 -04:00
Thomas Harte	421bf28582	Add comments, correct address decoding.	2025-09-18 12:27:13 -04:00
Thomas Harte	4c49ffe3d1	Attmept full ADC implementation.	2025-09-18 12:21:25 -04:00
Thomas Harte	26b1ef247b	Add calls to ADB.	2025-09-17 23:11:48 -04:00
Thomas Harte	ae774e88fa	Add header for ADC.	2025-09-17 21:42:42 -04:00
Thomas Harte	12f063c178	Hack in a stable sync.	2025-09-17 21:35:41 -04:00
Thomas Harte	1e90387198	Add extra curly brackets.	2025-09-16 16:25:29 -04:00
Thomas Harte	ff69709926	Disable interlace support.	2025-09-15 23:53:36 -04:00
Thomas Harte	2162822cec	Eliminate C++23 extension.	2025-09-15 23:42:57 -04:00
Thomas Harte	0d1fe03369	Further prefer static constexpr.	2025-09-12 21:40:08 -04:00
Thomas Harte	105272630e	Definitively eliminate per-logger state.	2025-09-11 23:29:47 -04:00
Thomas Harte	691292501a	Promote constexprs to static.	2025-09-10 21:46:44 -04:00
Thomas Harte	4b50c8d96c	Toy with sense interrupt status being directly seek-linked.	2025-09-02 17:50:59 -04:00
Thomas Harte	ac204aadd2	Clean up, better constify SCSI innards.	2025-08-31 10:56:01 -04:00
Thomas Harte	62f23ac27c	Commute macros.	2025-08-30 10:34:49 -04:00
Thomas Harte	0936646ef9	Eliminate macros.	2025-08-30 10:29:53 -04:00
Thomas Harte	d825c03372	Prefer references for delegate protocols.	2025-08-30 00:09:38 -04:00
Thomas Harte	d177549dd6	Reduce more indentation.	2025-08-29 23:56:35 -04:00
Thomas Harte	5018d7d577	Be more rigorous about static constexpr.	2025-08-26 22:54:39 -04:00
Thomas Harte	88e776ad5b	Use <algorithm>, and otherwise reduce.	2025-07-19 21:37:03 -04:00
Thomas Harte	5350e41da1	Switch to mildly-more-modern template form.	2025-05-02 13:50:06 -04:00