9 Commits

Author	SHA1	Message	Date
Thomas Harte	2a14557478	Be more disciplined about errant accesses.	2024-03-28 21:31:07 -04:00
Thomas Harte	0ddbc67b1f	Switch to default CMOS RAM obtained from RISC OS itself.	2024-03-28 21:23:49 -04:00
Thomas Harte	ffb5149890	Reinstate real CMOS RAM results.	2024-03-28 14:27:07 -04:00
Thomas Harte	4fcb85d132	Cleave off most remaining reasons for failure.	2024-03-28 10:32:27 -04:00
Thomas Harte	8b04d0e3ef	Enhance and better-document I2C states.	2024-03-26 21:52:29 -04:00
Thomas Harte	a3931674dc	Seemingly navigate I2C correctly.	2024-03-26 21:33:46 -04:00
Thomas Harte	3ba12630ab	Quieten.	2024-03-26 12:27:37 -04:00
Thomas Harte	342d90c929	Advance CMOS/I2C to a seemingly-valid read.	2024-03-26 12:24:24 -04:00
Thomas Harte	1341816791	Break apart, switching to delegates for interrupts.	2024-03-20 14:26:56 -04:00