21 Commits

Author	SHA1	Message	Date
Thomas Harte	189dd176de	Reguess state machine, fixing startup display.	2024-03-23 21:38:35 -04:00
Thomas Harte	c720f3910a	Avoid implicit sign cast.	2024-03-23 20:13:25 -04:00
Thomas Harte	58bbce1a15	Avoid display errors upon back-pressure.	2024-03-22 22:01:12 -04:00
Thomas Harte	de7b7818f4	Add 4bpp output.	2024-03-22 10:18:25 -04:00
Thomas Harte	c4e6b18294	Manage pixel buffers.	2024-03-22 10:10:13 -04:00
Thomas Harte	ae6cf69449	Move responsibility for clock division; reinstate vsync interrupt.	2024-03-22 10:01:34 -04:00
Thomas Harte	4a2dcff028	Endeavour to map colours properly.	2024-03-21 21:53:50 -04:00
Thomas Harte	aa6acec8fa	Don't hoard cycles per line value.	2024-03-21 21:47:27 -04:00
Thomas Harte	4ac4da908c	Reduce TODOs, do _something_ with border colour.	2024-03-21 21:40:11 -04:00
Thomas Harte	66e62857c4	Give ostensibly clean timing to the CRT.	2024-03-21 21:29:53 -04:00
Thomas Harte	bbc0d8b050	Count time in phase correctly.	2024-03-21 21:15:25 -04:00
Thomas Harte	0f8bc416d1	Make first, faulty step into displaying a field.	2024-03-21 21:10:55 -04:00
Thomas Harte	2ec235170e	Finish the thought on magic constants.	2024-03-21 20:45:17 -04:00
Thomas Harte	2de1a2dd0d	Install and properly clock a CRT.	2024-03-21 20:41:24 -04:00
Thomas Harte	1f49c3b113	Give sound and video somewhere to read from.	2024-03-21 20:22:20 -04:00
Thomas Harte	5c645fb3c2	Switch to a fixed output clock; retain addresses.	2024-03-21 11:51:29 -04:00
Thomas Harte	40b5227f0b	Deliver all addresses to the video outputter.	2024-03-21 11:24:47 -04:00
Thomas Harte	847dba8f07	Divide input pixel rate.	2024-03-21 11:03:28 -04:00
Thomas Harte	2d6a4d490e	Add dummy retrace interrupt.	2024-03-21 10:02:56 -04:00
Thomas Harte	389541be6d	Pipe further sound parameters; obey divider.	2024-03-20 14:43:47 -04:00
Thomas Harte	1341816791	Break apart, switching to delegates for interrupts.	2024-03-20 14:26:56 -04:00