Thomas Harte
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37950143fc
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Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
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2017-07-27 20:17:13 -04:00 |
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Thomas Harte
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108da64562
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Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
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2017-06-20 22:25:00 -04:00 |
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Thomas Harte
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184b371649
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Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
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2017-06-20 21:48:50 -04:00 |
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Thomas Harte
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27ac342928
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Corrected conditional call timing, and its test.
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2017-06-20 20:57:23 -04:00 |
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Thomas Harte
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6752f165db
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Added failing tests for both kinds of CALL.
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2017-06-19 22:03:29 -04:00 |
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Thomas Harte
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e05076b258
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Added tests for everything except CALL. All passing.
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2017-06-19 22:00:04 -04:00 |
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Thomas Harte
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fadbfdf801
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Added DJNZ test.
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2017-06-19 21:31:56 -04:00 |
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Thomas Harte
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cb277b8d1e
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Added JP and JR tests.
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2017-06-19 21:27:23 -04:00 |
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Thomas Harte
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234f14dbbe
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Tests were at fault; all passing now.
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2017-06-19 21:14:40 -04:00 |
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Thomas Harte
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99ede3a9ef
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BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
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2017-06-19 21:04:14 -04:00 |
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Thomas Harte
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378233f53d
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Extended to BITs and SETs, accruing three new failures.
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2017-06-19 21:01:30 -04:00 |
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Thomas Harte
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f903408980
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Caught up on comments.
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2017-06-19 20:53:22 -04:00 |
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Thomas Harte
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b684254908
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Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
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2017-06-19 20:33:34 -04:00 |
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Thomas Harte
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351d90ca55
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Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.
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2017-06-19 20:04:55 -04:00 |
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Thomas Harte
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23177df26a
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Added various tests of the basic ALU ops.
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2017-06-19 19:53:26 -04:00 |
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Thomas Harte
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ba15371948
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Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
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2017-06-19 19:47:00 -04:00 |
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Thomas Harte
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8d60734737
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Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
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2017-06-19 19:17:54 -04:00 |
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Thomas Harte
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002098d496
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The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
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2017-06-19 07:45:41 -04:00 |
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Thomas Harte
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85c5c4405a
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Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
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2017-06-19 07:30:01 -04:00 |
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Thomas Harte
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50cd617bd9
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Ensured test raises only the intentional failure exceptions.
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2017-06-15 22:33:46 -04:00 |
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Thomas Harte
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838b818cd3
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Finished transcribing first page of machine cycle documentation; several failures contained.
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2017-06-15 22:19:49 -04:00 |
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Thomas Harte
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cf795562bf
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Continued filling in tests, fleshing out what the test machine captures as a result.
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2017-06-15 20:59:59 -04:00 |
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Thomas Harte
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ac37424878
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Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
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2017-06-15 19:06:59 -04:00 |
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