Thomas Harte
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570d25214e
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Made an initial attempt at typer support for the CPC.
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2017-08-11 11:21:07 -04:00 |
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Thomas Harte
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6a65c7a52a
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Started working on a CPC-oriented analyser; for now I just want to be able to make a good guess at the appropriate file to load from a disk. As it turns out, the CPC simply adopts the CP/M format, so a generic parser is appropriate. This is its beginning.
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2017-08-10 17:10:21 -04:00 |
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Thomas Harte
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ad8c8166bc
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Built in gamma conversion for all machines, assuming an output of 2.8 for PAL, 2.2 for NTSC.
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2017-08-10 15:17:08 -04:00 |
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Thomas Harte
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4d60b8801c
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Started trying to factor out just the PLL stream -> FM/MFM events part that is presently in the WD1770.
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2017-08-05 22:26:15 -04:00 |
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Thomas Harte
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3e984e75b6
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Strung up an empty shell that eventually should contain the 8272, and added appropriate IO decoding to the Amstrad.
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2017-08-05 19:45:52 -04:00 |
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Thomas Harte
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75c59fefab
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Added an empty husk to begin support for Amstrad CPC disk image formats.
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2017-08-05 10:02:10 -04:00 |
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Thomas Harte
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bbb17acf3a
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Expanded interface so that an external machine caller can request a string be typed without any knowledge of whatever it intends to do re: CharacterMappers. Which is immediately useful in paste functionality.
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2017-08-03 11:50:50 -04:00 |
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Thomas Harte
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ad3a98387f
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Within the Typer framework: hatched out CharacterMapper as a distinct thing from the target for keypresses, better to formalise responsibility but also to make it easy cleanly to sever that stuff into its own little part.
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2017-08-03 11:42:31 -04:00 |
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Thomas Harte
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681d1e2f8d
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Breaking its typer for now, adapted the ZX80/81 to having a Z80, not being one.
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2017-08-02 22:12:59 -04:00 |
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Thomas Harte
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6ca07f1e28
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I guess it might end up living somewhere else, but introduced a header with the compiler-specific stuff to allow me to force things inline.
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2017-08-01 22:04:58 -04:00 |
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Thomas Harte
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9d43784c65
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Significantly increased quantity of keys forwarded.
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2017-08-01 20:37:55 -04:00 |
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Thomas Harte
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f5b278d683
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Added enough stuff to put the emulated Amstrad CPC in a state of knowing whether its '0' key is pressed.
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2017-08-01 17:31:56 -04:00 |
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Thomas Harte
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08ad35efd9
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It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC.
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2017-08-01 16:34:13 -04:00 |
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Thomas Harte
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58b98267fc
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Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
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2017-08-01 16:15:19 -04:00 |
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Thomas Harte
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ace71280a0
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Removed implementation file; this is only ever going to be a template.
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2017-08-01 16:00:17 -04:00 |
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Thomas Harte
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2b168f7383
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Disabled the address sanitiser as an every-time run again, as it just pushes my computer a bit too far.
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2017-07-31 22:32:56 -04:00 |
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Thomas Harte
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0536f089e1
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Eliminated old-[personal-]fashioned line break.
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2017-07-31 22:32:26 -04:00 |
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Thomas Harte
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3df13cddd4
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As per my keenness for cleanliness improvements corresponding to my ever-increasing C++ ability: turned the Amstrad into something that a factory produces, allowing me completely to hide a bunch of implementation details.
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2017-07-31 22:32:04 -04:00 |
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Thomas Harte
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68ceeab610
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Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
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2017-07-31 19:56:59 -04:00 |
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Thomas Harte
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afd409c883
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Ensured that ROM images are loaded and passed to the Amstrad CPC.
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2017-07-31 18:44:49 -04:00 |
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Thomas Harte
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26b6c03a2a
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Re-enabled the address sanitiser as a development tool.
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2017-07-31 07:30:07 -04:00 |
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Thomas Harte
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c0f1313830
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Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT.
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2017-07-30 22:05:29 -04:00 |
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Thomas Harte
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5b5720fac0
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Added to the static analyser the most basic through-path for Amstrad CPC content.
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2017-07-30 21:15:20 -04:00 |
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Thomas Harte
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d25d7d7d40
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Added the Amstrad CPC as a named target and declared support for its CDT file format.
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2017-07-29 21:56:33 -04:00 |
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Thomas Harte
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761afad118
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Corrected timestamp return, and its testing by the 6502 timing tests.
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2017-07-27 21:19:16 -04:00 |
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Thomas Harte
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37950143fc
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Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
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2017-07-27 20:17:13 -04:00 |
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Thomas Harte
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9257a3f6d7
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Added test for 16-bit arithmetic, and fixed implementation.
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2017-07-26 19:04:52 -04:00 |
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Thomas Harte
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728143247d
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Added a test for RLD and RRD. Which already passes.
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2017-07-26 18:56:35 -04:00 |
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Thomas Harte
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6ec4e4e3d7
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Merge branch 'master' into Memptr
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2017-07-25 23:01:34 -04:00 |
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Thomas Harte
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37ccb9d3b6
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Fixed 6502 timing tests.
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2017-07-25 23:00:39 -04:00 |
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Thomas Harte
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3c254360ba
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Completed fixture of the 6502 BCD test.
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2017-07-25 22:55:45 -04:00 |
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Thomas Harte
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3ca51bedc6
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Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses.
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2017-07-25 22:48:44 -04:00 |
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Thomas Harte
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36076b7ea5
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Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams.
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2017-07-25 22:38:26 -04:00 |
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Thomas Harte
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279c369a1f
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Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
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2017-07-25 22:21:09 -04:00 |
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Thomas Harte
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75d67ee770
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Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
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2017-07-25 20:20:55 -04:00 |
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Thomas Harte
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df4732be2e
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Corrected test.
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2017-07-24 22:33:49 -04:00 |
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Thomas Harte
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9435c1e12a
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The 1540 is now a ClockReceiver.
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2017-07-24 22:32:41 -04:00 |
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Thomas Harte
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2912d7055b
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The 6532 is now a ClockReceiver.
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2017-07-24 21:57:24 -04:00 |
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Thomas Harte
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13f7aa4063
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The TIA is now a ClockReceiver.
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2017-07-24 21:48:34 -04:00 |
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Thomas Harte
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b3ae920746
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Converted the DPLL and disk controller classes to be ClockReceivers.
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2017-07-24 21:04:47 -04:00 |
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Thomas Harte
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e6578defcd
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It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.
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2017-07-23 22:22:50 -04:00 |
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Thomas Harte
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ace8e30818
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Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
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2017-07-23 22:21:39 -04:00 |
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Thomas Harte
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b0c2325adc
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Corrected run call, and accepted that jam handling is gone forever.
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2017-07-22 22:21:26 -04:00 |
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Thomas Harte
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2ff157cf7a
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Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.
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2017-07-22 22:17:29 -04:00 |
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Thomas Harte
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1ba3f262a2
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Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.
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2017-07-22 21:46:50 -04:00 |
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Thomas Harte
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4ea835e50b
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Added test for EX (SP), rp, which passes.
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2017-07-22 17:17:32 -04:00 |
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Thomas Harte
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5fddbec132
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Merge branch 'master' into Memptr
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2017-07-22 17:06:22 -04:00 |
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Thomas Harte
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6633537fb8
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Discovering that there is such a thing as P81 — a ZX81 file without the name omitted — added support for it. Extended FileHolder while I was here to retain the file name and be able to supply its extension, as my quick-fix test-the-last-character approach to o/p/80/81 discrimination stops working with p81 thrown into the mix and this feels like the correct factoring.
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2017-07-22 16:02:25 -04:00 |
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Thomas Harte
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6437c43147
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Added CPI and CPD tests: at last two that pass without requiring implementation changes!
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2017-07-22 12:38:18 -04:00 |
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Thomas Harte
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5928a24803
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Transcribed missing tests as TODOs.
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2017-07-22 11:44:17 -04:00 |
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Thomas Harte
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20a6bcc676
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Added tests for the various LD (nn), rr instructions and corrected implementation to pass.
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2017-07-22 11:39:13 -04:00 |
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Thomas Harte
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eaf313b0f6
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Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
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2017-07-22 11:20:21 -04:00 |
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Thomas Harte
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d51b66c204
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Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
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2017-07-21 23:01:35 -04:00 |
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Thomas Harte
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660f0e4c40
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Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.
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2017-07-21 22:52:25 -04:00 |
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Thomas Harte
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2b5d0877a8
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Adjusted parameter name to match documentation. I think it's a carry-over from before I was passing the whole event along.
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2017-07-21 21:27:50 -04:00 |
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Thomas Harte
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2a7fc86b15
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Enabled stricter warnings.
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2017-07-21 20:44:35 -04:00 |
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Thomas Harte
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8f72fc4a44
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Factored out from the UEF implementation the concept of being a tape that has a queue of pending pulses and manages that queue.
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2017-07-16 22:04:40 -04:00 |
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Thomas Harte
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238348c885
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Performed the initial wiring to announce that this application supports TZX files and to route them to the ZX80/81 static analyser. The TZX class itself does not yet do much beyond basic validation. I think it'll be easiest if it follows in UEF's footsteps in queuing up pulses ahead of time, so some factoring out is now required.
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2017-07-16 21:33:11 -04:00 |
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Thomas Harte
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7b5f93510b
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Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.
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2017-07-16 20:55:57 -04:00 |
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Thomas Harte
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8ddd686049
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Removed redundant variable.
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2017-07-16 19:04:03 -04:00 |
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Thomas Harte
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2fb0aea990
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Updated the C1540 test vessel to the new world.
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2017-07-16 17:00:39 -04:00 |
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Thomas Harte
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279f4760d7
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Eliminated buffer_size_ as something explicitly stored, and reduced size of delegate call out.
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2017-07-16 15:01:39 -04:00 |
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Thomas Harte
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368bff1a82
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Added a shell class that will one day be able to parse CSW files, plus the logic and metadata to instantiate it when a CSW presents itself.
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2017-07-10 21:43:58 -04:00 |
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Thomas Harte
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3e5c209039
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Added basic Typer support for the ZX80 and '81.
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2017-07-09 22:00:34 -04:00 |
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Thomas Harte
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54efcb7e2f
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Made a game attempt at automatic motor control and ensured setting is initialised correctly from the user defaults.
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2017-07-08 19:31:20 -04:00 |
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Thomas Harte
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e2575d6de4
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Routed tape motor selections through to the C++ side of the world, and ensured that manual tape playback works properly.
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2017-07-08 19:21:12 -04:00 |
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Thomas Harte
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23e989e170
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This will likely do for the Swift/XIB side of things: the play/pause button is enabled or disabled as per the user's choice of automatic tape control, and toggles function when pressed. It communicates activity down to the Objective-C[++] layer, giving it a route through to the actual machine.
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2017-07-08 19:12:06 -04:00 |
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Thomas Harte
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28412150e6
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Added controls for controlling the tape motor of the ZX80/81, assuming I can find an automatic option.
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2017-07-08 17:59:33 -04:00 |
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Thomas Harte
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cb105fdeb4
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Took a first stab at high-res support.
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2017-06-22 22:48:17 -04:00 |
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Thomas Harte
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aec4fd066b
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I think I've definitively decided against this model of timing.
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2017-06-22 21:32:14 -04:00 |
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Thomas Harte
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95a6b0f85c
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Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
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2017-06-22 21:09:26 -04:00 |
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Thomas Harte
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644ef13acd
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Connected up the fast-tape GUI option for the ZX80 and '81.
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2017-06-22 20:20:31 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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108da64562
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Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
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2017-06-20 22:25:00 -04:00 |
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Thomas Harte
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184b371649
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Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
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2017-06-20 21:48:50 -04:00 |
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Thomas Harte
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27ac342928
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Corrected conditional call timing, and its test.
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2017-06-20 20:57:23 -04:00 |
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Thomas Harte
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6752f165db
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Added failing tests for both kinds of CALL.
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2017-06-19 22:03:29 -04:00 |
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Thomas Harte
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e05076b258
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Added tests for everything except CALL. All passing.
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2017-06-19 22:00:04 -04:00 |
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Thomas Harte
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fadbfdf801
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Added DJNZ test.
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2017-06-19 21:31:56 -04:00 |
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Thomas Harte
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cb277b8d1e
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Added JP and JR tests.
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2017-06-19 21:27:23 -04:00 |
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Thomas Harte
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234f14dbbe
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Tests were at fault; all passing now.
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2017-06-19 21:14:40 -04:00 |
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Thomas Harte
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99ede3a9ef
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BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
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2017-06-19 21:04:14 -04:00 |
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Thomas Harte
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378233f53d
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Extended to BITs and SETs, accruing three new failures.
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2017-06-19 21:01:30 -04:00 |
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Thomas Harte
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f903408980
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Caught up on comments.
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2017-06-19 20:53:22 -04:00 |
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Thomas Harte
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b684254908
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Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
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2017-06-19 20:33:34 -04:00 |
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Thomas Harte
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351d90ca55
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Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.
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2017-06-19 20:04:55 -04:00 |
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Thomas Harte
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23177df26a
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Added various tests of the basic ALU ops.
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2017-06-19 19:53:26 -04:00 |
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Thomas Harte
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ba15371948
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Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
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2017-06-19 19:47:00 -04:00 |
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Thomas Harte
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8d60734737
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Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
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2017-06-19 19:17:54 -04:00 |
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Thomas Harte
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002098d496
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The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
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2017-06-19 07:45:41 -04:00 |
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Thomas Harte
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85c5c4405a
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Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
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2017-06-19 07:30:01 -04:00 |
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Thomas Harte
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d668879ba6
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Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
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2017-06-18 22:03:13 -04:00 |
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Thomas Harte
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e1a2580b2a
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Renamed BusOperation to MachineCycle::Operation.
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2017-06-17 21:53:45 -04:00 |
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Thomas Harte
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b6f51474ff
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Ensured that -description can handle the newly-captured bus actions.
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2017-06-17 18:20:30 -04:00 |
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Thomas Harte
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0f18768091
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Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.
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2017-06-17 18:19:25 -04:00 |
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Thomas Harte
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50cd617bd9
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Ensured test raises only the intentional failure exceptions.
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2017-06-15 22:33:46 -04:00 |
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Thomas Harte
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838b818cd3
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Finished transcribing first page of machine cycle documentation; several failures contained.
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2017-06-15 22:19:49 -04:00 |
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Thomas Harte
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cf795562bf
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Continued filling in tests, fleshing out what the test machine captures as a result.
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2017-06-15 20:59:59 -04:00 |
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Thomas Harte
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ac37424878
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Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
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2017-06-15 19:06:59 -04:00 |
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