Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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37950143fc
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Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
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2017-07-27 20:17:13 -04:00 |
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Thomas Harte
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8361756dc4
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Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
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2017-07-27 07:40:02 -04:00 |
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Thomas Harte
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279c369a1f
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Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
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2017-07-25 22:21:09 -04:00 |
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Thomas Harte
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75d67ee770
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Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
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2017-07-25 20:20:55 -04:00 |
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Thomas Harte
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a1e9a54765
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Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
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2017-07-25 20:09:13 -04:00 |
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Thomas Harte
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677ed463f0
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Updated comment per new method name.
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2017-07-24 21:19:49 -04:00 |
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Thomas Harte
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b82bef95f3
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Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
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2017-07-24 20:10:05 -04:00 |
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Thomas Harte
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2ff157cf7a
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Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.
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2017-07-22 22:17:29 -04:00 |
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Thomas Harte
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83628b285b
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Experimentally turned the 6502 into a clock receiver. No problem encountered.
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2017-07-22 21:52:21 -04:00 |
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Thomas Harte
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1a811b1ab1
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Eliminated the function call inherent to every decode, and also moved the fixed table of operations into a non-templated base class.
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2017-06-03 22:19:35 -04:00 |
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Thomas Harte
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c26349624c
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This, of course, should be inline to gain any benefit from the slightly-tortured private implementation.
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2017-06-03 22:00:57 -04:00 |
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Thomas Harte
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b642d9f712
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Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
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2017-06-03 21:54:42 -04:00 |
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Thomas Harte
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fd6623b5a5
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Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
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2017-06-03 21:22:16 -04:00 |
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Thomas Harte
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b304c3a4b9
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Eliminated the 6502's reliance on the micro-op scheduler.
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2017-06-03 20:30:07 -04:00 |
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Thomas Harte
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01f7394f7f
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Corrected 6502 scheduling when flushing the pipeline.
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2017-05-30 20:58:07 -04:00 |
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Thomas Harte
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5aa8b03349
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Attempted to regularise the 6502 with the Z80 as to scheduling. I think that at least one bug remains.
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2017-05-30 20:36:53 -04:00 |
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Thomas Harte
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a0189a6fe1
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Switched to following the current program via address.
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2017-05-30 18:49:40 -04:00 |
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Thomas Harte
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21d0602305
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Restored the all RAM 6502's lack of power-on reset.
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2017-05-17 21:43:40 -04:00 |
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Thomas Harte
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7190f927b7
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Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
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2017-05-16 21:28:17 -04:00 |
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Thomas Harte
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d559d8b901
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Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
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2017-05-16 21:19:17 -04:00 |
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Thomas Harte
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eb8a2de5d6
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Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
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2017-05-15 07:38:59 -04:00 |
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Thomas Harte
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0808e9b6fb
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Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.
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2017-05-14 22:08:15 -04:00 |
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Thomas Harte
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b81a2cc273
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First tentative steps towards adding a Z80 implementation.
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2017-05-14 17:46:41 -04:00 |
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Thomas Harte
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defec2c9b0
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Fixed: operation reads now fulfil the promise of seeding the value to be read with 0xff.
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2017-03-26 20:56:27 -04:00 |
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Thomas Harte
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e01f3f06c8
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Completed curly bracket movement.
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2017-03-26 14:34:47 -04:00 |
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Thomas Harte
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55ce851bb2
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Fixed types of the 8k cartridges, ensured the 6502 starts without an IRQ request history.
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2017-03-18 17:04:01 -04:00 |
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Thomas Harte
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36b58d03b7
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Formalised read bus value guarantee from the 6502, fixed missing clock signal wiring on the Atari cartridge class, reintroduced CommaVid support.
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2017-03-18 14:46:46 -04:00 |
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Thomas Harte
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14a76af0d3
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Started trying to float out bus control to cartridges.
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2017-03-17 20:28:07 -04:00 |
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Thomas Harte
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5be22e2f8d
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Switched to suffix underscores and underscores in general for instance variables.
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2016-12-03 11:38:53 -05:00 |
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Thomas Harte
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7ad44f5152
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Flipped order of conditional so as negligibly to improve prediction.
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2016-10-31 22:17:18 -04:00 |
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Thomas Harte
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2452a3104f
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Corrected test: hitting zero is sufficient. No need to cross it.
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2016-10-30 20:24:30 -04:00 |
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Thomas Harte
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9309be229c
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Moved cycle count test down to the only places where it may actually yield a different result.
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2016-10-30 20:13:44 -04:00 |
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Thomas Harte
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a106018680
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Fixed initial state: interrupt flag is initially low.
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2016-10-28 21:22:03 -04:00 |
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Thomas Harte
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613b5b3f98
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Switched to inverse storage of the interrupt flag so as to reduce logical burden when storing IRQ line history.
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2016-10-28 20:52:43 -04:00 |
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Thomas Harte
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4408c60ef7
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This too should continue, not break, since it doesn't schedule a memory access.
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2016-10-27 18:32:21 -04:00 |
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Thomas Harte
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534b3d085d
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Improved test reporting, attempted to resolve timing errors just introduced (i.e. to differentiate break/continue where a cycle may or may not be spent).
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2016-10-27 08:41:44 -04:00 |
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Thomas Harte
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f84b66a5f4
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Made an attempt to fix wake-from-WAIT.
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2016-10-25 19:06:46 -04:00 |
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Thomas Harte
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4b18c76b84
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Introduced a bifurcation between break and continue to signify whether a bus access takes place, necessitating a shift in the location of the bus access but allowing the conditional to be dropped. Need to test.
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2016-10-25 18:45:53 -04:00 |
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Thomas Harte
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c253a4258f
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Made minor restructuring changes, slightly to reduce number of conditionals per operation and to drop a big hint to the optimiser.
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2016-10-25 18:34:24 -04:00 |
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Thomas Harte
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fa7c64bb5d
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Eventually reached an implementation of ADC that continues to satisfy all the formalised unit tests while also satisfying the manual BCDTest, that I need to find a way to formalise. I fixed the unit tests for Swift 3 while here, and attempted to do some unrelated NIB stuff with no real success.
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2016-10-03 22:03:39 -04:00 |
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Thomas Harte
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5d40d70c92
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Fixed 6560 addressing error, added an autotyper for Vic disks (more work potentially needed), fixed semantics for testing whether a 6502 is about to reset.
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2016-08-01 10:32:32 -04:00 |
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Thomas Harte
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740ea0b7e2
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Added overflow-flag setting logic and ensured disk ROM gets through regardless of ROM/disk installation order.
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2016-07-31 19:33:18 -04:00 |
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Thomas Harte
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1baf21827c
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Since the ROM is well disassembled, let's actually try to be a 1541 first.
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2016-07-06 22:17:32 -04:00 |
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Thomas Harte
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41809d4597
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Made an attempt at NMI usurption of IRQ/BRK.
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2016-06-29 20:59:45 -04:00 |
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Thomas Harte
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c02226bc41
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Ensured stack pointer goes the right way upon reset.
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2016-06-29 20:42:26 -04:00 |
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Thomas Harte
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db7c6430b5
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Fixed Klaus Dormann termination condition.
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2016-06-29 19:16:34 -04:00 |
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Thomas Harte
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0182b0483a
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Added a 'power on' flag that is set automatically at construction but can be declined. Saves all that stuff of every machine having to set and then unset the RST line, and fixes an Electron bug related to that.
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2016-06-29 19:13:24 -04:00 |
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Thomas Harte
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6419d9c485
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Added a single IRQ test case, discovering that I'm two cycles short. Whoops!
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2016-06-28 21:29:43 -04:00 |
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Thomas Harte
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6e698e908e
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Made an attempt to reduce cost of the most-likely path.
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2016-06-28 18:46:00 -04:00 |
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