 Thomas Harte
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a4a0026cab
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Reintroduce decay stage; flip pulse meaning.
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2025-11-11 21:38:27 -05:00 |
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Thomas Harte
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eac7493180
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Support master volume.
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2025-11-11 21:04:07 -05:00 |
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Thomas Harte
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989fb32fba
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Fix clocking, do a linear attack phase.
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2025-11-11 20:53:54 -05:00 |
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Thomas Harte
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735afcfabb
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Adopt painful pulse test, temporarily (?).
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2025-11-11 18:26:00 -05:00 |
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Thomas Harte
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37152a1fad
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Start testing; I'm now unsure about pulses.
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2025-11-11 17:54:31 -05:00 |
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Thomas Harte
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4e86184955
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Add local hack to ensure good flushing.
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2025-11-11 14:40:13 -05:00 |
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Thomas Harte
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d23dbb96c2
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Support system volume, avoid clipping.
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2025-11-11 14:40:04 -05:00 |
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Thomas Harte
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4586e4b4c1
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Apply envelope.
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2025-11-11 14:26:53 -05:00 |
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Thomas Harte
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de5cdbf18c
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Make a complete attempt at ADSR.
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2025-11-11 14:25:36 -05:00 |
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Thomas Harte
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8c2294fc0d
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Treat sustain as a volume; start second prescaler table.
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2025-11-11 12:43:48 -05:00 |
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Thomas Harte
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b0b82782ad
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Build in initial prescaler.
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2025-11-11 12:21:49 -05:00 |
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Thomas Harte
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b9f5802c89
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Return whatever was written last if read.
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2025-11-11 09:19:01 -05:00 |
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Thomas Harte
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29235f1276
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Adjust noise clocking, make it reactive to the test bit.
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2025-11-11 09:16:43 -05:00 |
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Thomas Harte
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8c74e2a323
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Implement LFSR.
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2025-11-10 22:44:00 -05:00 |
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Thomas Harte
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ae2936b9c3
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Correct clock rate, triangle wave.
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2025-11-10 22:35:13 -05:00 |
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Thomas Harte
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0d295a6338
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Don't capture a reference to parameters.
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2025-11-10 22:10:28 -05:00 |
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Thomas Harte
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3ebd6c6871
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Rejig oscillators, output some vague noise.
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2025-11-10 21:52:10 -05:00 |
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Thomas Harte
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6e2cd0ace6
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Divide state, start adding waveforms.
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2025-11-10 17:27:32 -05:00 |
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Thomas Harte
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af82a0bcda
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Add ADSR TODO.
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2025-11-10 14:18:24 -05:00 |
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Thomas Harte
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6fe208ae77
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Honour test and sync bits.
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2025-11-10 14:17:54 -05:00 |
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Thomas Harte
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f569b86c90
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Merge branch 'master' into BeebSID
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2025-11-10 14:10:33 -05:00 |
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 Thomas Harte
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b622cc9536
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Merge pull request #1635 from TomHarte/CleanerQueue
Enforce perform_automatically, start_immediately; relax Boolean access order.
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2025-11-10 14:09:31 -05:00 |
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Thomas Harte
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7dfd5ea0d0
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Add phase accumulation, rename to pitch.
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2025-11-10 13:27:43 -05:00 |
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Thomas Harte
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a81309433c
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Switch to lambda form.
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2025-11-09 21:09:57 -05:00 |
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Thomas Harte
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902f388cb1
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Enforce perform_automatically, start_immediately; relax Boolean access order.
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2025-11-09 00:17:39 -05:00 |
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Thomas Harte
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0cc5a9d74f
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Move thread.
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2025-11-08 23:02:54 -05:00 |
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Thomas Harte
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5e98e6502d
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Attempt some basic voice details.
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2025-11-08 21:54:41 -05:00 |
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Thomas Harte
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fe7a206fc5
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Add an empty vessel of a SID.
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2025-11-07 22:51:28 -05:00 |
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Thomas Harte
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c5704aaaff
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Merge pull request #1633 from TomHarte/TubeBrevity
Move point of templature to tube processors.
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2025-11-07 18:05:19 -05:00 |
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Thomas Harte
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e115f09f51
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Merge pull request #1632 from TomHarte/6845DeadState
Remove dead state.
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2025-11-07 17:54:13 -05:00 |
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Thomas Harte
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32cd142629
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Move point of templature to tube processors.
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2025-11-07 17:27:52 -05:00 |
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Thomas Harte
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b00be303aa
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Remove dead state.
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2025-11-07 13:08:12 -05:00 |
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Thomas Harte
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273e23bd98
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Merge pull request #1631 from TomHarte/SecondProcessorScreenshot
Substitute a screenshot of Second Processor Elite.
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2025-11-07 12:54:16 -05:00 |
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Thomas Harte
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5063e6943d
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Substitute a screenshot of Second Processor Elite.
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2025-11-07 12:53:09 -05:00 |
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Thomas Harte
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ce32747973
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Record new version number.
2025-11-07
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2025-11-07 12:39:46 -05:00 |
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Thomas Harte
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a8ef8dfb21
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Merge pull request #1630 from TomHarte/DNFS
Add DFS 0.9 to ROM catalogue; restrict CRTC pointer size.
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2025-11-07 11:19:21 -05:00 |
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Thomas Harte
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7658edca62
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Remove unused enum.
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2025-11-07 10:49:26 -05:00 |
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Thomas Harte
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056028e07b
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Put bit restriction on register pointer.
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2025-11-07 10:43:14 -05:00 |
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Thomas Harte
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34992126a8
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Allow installation of smaller ROMs.
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2025-11-07 09:12:47 -05:00 |
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Thomas Harte
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d30d4e8f89
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Add DFS 0.9 to the ROM catalogue.
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2025-11-07 09:08:16 -05:00 |
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Thomas Harte
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f562deca48
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Record new version number.
2025-11-05
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2025-11-05 20:56:13 -05:00 |
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Thomas Harte
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b2b7aa221b
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Merge pull request #1629 from TomHarte/6502SecondAnalyser
Automatically add a 65c02 second processor if seemingly helpful.
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2025-11-05 20:51:44 -05:00 |
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Thomas Harte
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b98a9a8487
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Add automatic test for 6502 second processor.
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2025-11-05 20:40:29 -05:00 |
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Thomas Harte
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7f36a8a746
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Merge pull request #1628 from TomHarte/TubeResetLater
Give Tube ULA full ownership of parasite IRQ/NMI/reset.
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2025-11-05 15:41:50 -05:00 |
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Thomas Harte
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2fe6e9c7fc
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Reformulate to give ULA full IRQ/NMI/reset signalling duties.
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2025-11-05 15:27:11 -05:00 |
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Thomas Harte
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62919e77d4
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Reset at end.
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2025-11-05 15:11:49 -05:00 |
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Thomas Harte
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871b724290
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Merge pull request #1627 from TomHarte/TubeReset
Propagate system reset to the tube.
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2025-11-04 23:24:20 -05:00 |
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Thomas Harte
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ca23c04ba1
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Propagate system reset to the tube.
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2025-11-04 23:18:18 -05:00 |
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Thomas Harte
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44b8f75611
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Merge pull request #1626 from TomHarte/TubeSelection
Detect CP/M discs and route to the Z80 second processor.
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2025-11-04 23:11:31 -05:00 |
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Thomas Harte
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301df785fe
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Fix weird Os for 0s substitution.
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2025-11-04 23:11:06 -05:00 |
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