1612 Commits

Author	SHA1	Message	Date
Thomas Harte	7316fe00ee	Support native blink speeds.	2025-09-29 16:13:39 -04:00
Thomas Harte	f9e5b0f0c7	6522: avoid handshaking with register F.	2025-09-28 22:12:53 -04:00
Thomas Harte	622679f4c2	Slow flash rate (though it's probably asymmetrical?)	2025-09-27 07:58:11 -04:00
Thomas Harte	141d43d3e5	Further express smoothing in terms of pixel patterns.	2025-09-25 23:02:33 -04:00
Thomas Harte	823f7b1d2e	Attempt held graphics.	2025-09-25 22:47:13 -04:00
Thomas Harte	6579f011d0	Support flash and conceal.	2025-09-25 22:37:38 -04:00
Thomas Harte	93f768af9b	Bump control codes up in the roster.	2025-09-25 22:18:52 -04:00
Thomas Harte	26ccd930c3	Begin tidying.	2025-09-25 17:53:54 -04:00
Thomas Harte	82211c7312	Add some 'graphics' support.	2025-09-25 17:50:26 -04:00
Thomas Harte	2015c154fe	Correctly clear double-height flags.	2025-09-25 13:28:22 -04:00
Thomas Harte	ef17d116a8	Don't permit single-height text on a lower double-height row.	2025-09-25 13:22:25 -04:00
Thomas Harte	46fddc44bf	Support double-height text.	2025-09-25 13:21:49 -04:00
Thomas Harte	425ed658f1	Support colour control codes, clarify SAA5050 signalling.	2025-09-25 13:03:55 -04:00
Thomas Harte	3c3c55090a	Port forward ElectrEm's font smoothing.	2025-09-25 09:22:16 -04:00
Thomas Harte	8b0e8f5b13	Move all work [near] definitively into the SAA5050.	2025-09-24 22:55:49 -04:00
Thomas Harte	b6e41ceea7	Hack in low-resolution Mode 7.	2025-09-24 22:25:43 -04:00
Thomas Harte	7015e46227	Put together enough of an interface to expect to see some pixels.	2025-09-24 22:08:04 -04:00
Thomas Harte	cce2607c80	Add file for SAA5050 logic.	2025-09-24 21:43:25 -04:00
Thomas Harte	068726e0ab	Add TODO.	2025-09-24 21:26:04 -04:00
Thomas Harte	89e86ad9bd	Delay publication of the refresh address.	2025-09-24 21:20:20 -04:00
Thomas Harte	174c8dafbf	Resolve potential out-of-phase line counter.	2025-09-24 17:26:40 -04:00
Thomas Harte	90a96293de	Implement interlace-dependent row addressing.	2025-09-24 17:20:04 -04:00
Thomas Harte	84877c4fec	Reenable the cursor; good enough for now.	2025-09-24 14:37:52 -04:00
Thomas Harte	a7cceb5fa9	Avoid circular state dependency.	2025-09-24 14:30:37 -04:00
Thomas Harte	ca6359a597	Reintroduce pixels, proving myself to be off-by-one.	2025-09-24 14:29:25 -04:00
Thomas Harte	b7c3667be1	Work out inadvertent discrepancies.	2025-09-24 14:11:06 -04:00
Thomas Harte	b6dea59db3	This tests lines, not rows.	2025-09-24 13:56:16 -04:00
Thomas Harte	aa51f13743	Reorder to avoid dependencies upon values that mutate.	2025-09-24 13:54:09 -04:00
Thomas Harte	f34ec03ff0	Attempt to fix off-by-one; adopt fixed pixel pattern.	2025-09-24 13:42:17 -04:00
Thomas Harte	1363be59b7	Formalise field size.	2025-09-24 11:17:47 -04:00
Thomas Harte	622c24ef24	This indicates a line, not a row.	2025-09-23 22:36:56 -04:00
Thomas Harte	539b0e49d4	Start in mode 7, reallow interlaced modes.	2025-09-23 14:45:32 -04:00
Thomas Harte	0c42976312	Add notes to self.	2025-09-23 14:42:16 -04:00
Thomas Harte	67e1773495	This flag covers rows, not lines.	2025-09-23 14:29:00 -04:00
Thomas Harte	a199b64aa0	Clarify naming, attempt better to conform to FPGA precedent.	2025-09-23 14:27:21 -04:00
Thomas Harte	0349931953	Shuffle declare order.	2025-09-22 13:21:48 -04:00
Thomas Harte	d612a385d2	Dig in further on types.	2025-09-22 13:20:10 -04:00
Thomas Harte	ed4f299d55	Start formalising types.	2025-09-22 13:09:30 -04:00
Thomas Harte	66bfb86d42	Introduce SizedCounter as start of CRTC reworking.	2025-09-22 12:46:39 -04:00
Thomas Harte	fb5ef200fb	Correct uPD7002 interrupt wiring.	2025-09-20 21:51:19 -04:00
Thomas Harte	719a090b34	Retain bit 2.	2025-09-20 20:06:28 -04:00
Thomas Harte	3af85da6e0	Adjust conversion bits in status.	2025-09-20 19:52:47 -04:00
Thomas Harte	8fd62aa525	Disable interrupt at start of conversion.	2025-09-20 19:49:16 -04:00
Thomas Harte	eef0ee8180	Support cursor to end of row.	2025-09-20 08:27:58 -04:00
Thomas Harte	ff0ba7d48b	Reduce logging again.	2025-09-19 22:59:58 -04:00
Thomas Harte	3916ba1a42	This intermittently succeeds. Doubling down on investigation.	2025-09-19 20:33:02 -04:00
Thomas Harte	421bf28582	Add comments, correct address decoding.	2025-09-18 12:27:13 -04:00
Thomas Harte	4c49ffe3d1	Attmept full ADC implementation.	2025-09-18 12:21:25 -04:00
Thomas Harte	26b1ef247b	Add calls to ADB.	2025-09-17 23:11:48 -04:00
Thomas Harte	ae774e88fa	Add header for ADC.	2025-09-17 21:42:42 -04:00