8 Commits

Author	SHA1	Message	Date
Thomas Harte	c352d8ae8c	Adds a received_data_ register, that presently can never fill.	2019-10-13 23:04:57 -04:00
Thomas Harte	8d87e9eb1c	The ACIA actually has two clocks, though on an ST they're both 500,000 Hz.	2019-10-13 21:32:34 -04:00
Thomas Harte	f86dc082bb	Ensures serial lines know their writer's clock rate.	2019-10-13 20:41:08 -04:00
Thomas Harte	516d78f5a8	Attempts to implement transmission interrupts and ClockingHint::Source.	2019-10-12 23:46:57 -04:00
Thomas Harte	8b50a7d6e3	Attempts mostly to implement 6850 output.	2019-10-12 23:14:29 -04:00
Thomas Harte	4bf81d3b90	Decodes the 6850 control register, and starts working on standardised serial ports.	2019-10-12 18:19:55 -04:00
Thomas Harte	cd75978e4e	Nudges 6850 towards coherence.	2019-10-12 00:04:02 -04:00
Thomas Harte	d7ce2c26e8	Adds an empty shell for the ACIA.	2019-10-10 20:54:29 -04:00