635 Commits

Author	SHA1	Message	Date
Thomas Harte	aec4fd066b	I think I've definitively decided against this model of timing.	2017-06-22 21:32:14 -04:00
Thomas Harte	95a6b0f85c	Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.	2017-06-22 21:09:26 -04:00
Thomas Harte	644ef13acd	Connected up the fast-tape GUI option for the ZX80 and '81.	2017-06-22 20:20:31 -04:00
Thomas Harte	0e0ce379b4	Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.	2017-06-21 20:38:08 -04:00
Thomas Harte	36e8a11505	Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.	2017-06-21 20:32:08 -04:00
Thomas Harte	108da64562	Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.	2017-06-20 22:25:00 -04:00
Thomas Harte	184b371649	Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.	2017-06-20 21:48:50 -04:00
Thomas Harte	27ac342928	Corrected conditional call timing, and its test.	2017-06-20 20:57:23 -04:00
Thomas Harte	6752f165db	Added failing tests for both kinds of CALL.	2017-06-19 22:03:29 -04:00
Thomas Harte	e05076b258	Added tests for everything except CALL. All passing.	2017-06-19 22:00:04 -04:00
Thomas Harte	fadbfdf801	Added DJNZ test.	2017-06-19 21:31:56 -04:00
Thomas Harte	cb277b8d1e	Added JP and JR tests.	2017-06-19 21:27:23 -04:00
Thomas Harte	234f14dbbe	Tests were at fault; all passing now.	2017-06-19 21:14:40 -04:00
Thomas Harte	99ede3a9ef	BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).	2017-06-19 21:04:14 -04:00
Thomas Harte	378233f53d	Extended to BITs and SETs, accruing three new failures.	2017-06-19 21:01:30 -04:00
Thomas Harte	f903408980	Caught up on comments.	2017-06-19 20:53:22 -04:00
Thomas Harte	b684254908	Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.	2017-06-19 20:33:34 -04:00
Thomas Harte	351d90ca55	Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.	2017-06-19 20:04:55 -04:00
Thomas Harte	23177df26a	Added various tests of the basic ALU ops.	2017-06-19 19:53:26 -04:00
Thomas Harte	ba15371948	Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.	2017-06-19 19:47:00 -04:00
Thomas Harte	8d60734737	Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.	2017-06-19 19:17:54 -04:00
Thomas Harte	002098d496	The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.	2017-06-19 07:45:41 -04:00
Thomas Harte	85c5c4405a	Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.	2017-06-19 07:30:01 -04:00
Thomas Harte	d668879ba6	Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.	2017-06-18 22:03:13 -04:00
Thomas Harte	e1a2580b2a	Renamed BusOperation to MachineCycle::Operation.	2017-06-17 21:53:45 -04:00
Thomas Harte	b6f51474ff	Ensured that -description can handle the newly-captured bus actions.	2017-06-17 18:20:30 -04:00
Thomas Harte	0f18768091	Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.	2017-06-17 18:19:25 -04:00
Thomas Harte	50cd617bd9	Ensured test raises only the intentional failure exceptions.	2017-06-15 22:33:46 -04:00
Thomas Harte	838b818cd3	Finished transcribing first page of machine cycle documentation; several failures contained.	2017-06-15 22:19:49 -04:00
Thomas Harte	cf795562bf	Continued filling in tests, fleshing out what the test machine captures as a result.	2017-06-15 20:59:59 -04:00
Thomas Harte	ac37424878	Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.	2017-06-15 19:06:59 -04:00
Thomas Harte	aed2827e7b	Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.	2017-06-12 22:22:00 -04:00
Thomas Harte	a48616a138	Fixed reference to Swift-world MachineDocument for the ZX81 file type.	2017-06-12 18:51:11 -04:00
Thomas Harte	8222aac9e3	Added an official declaration of support for ZX81 files.	2017-06-11 21:40:41 -04:00
Thomas Harte	77aa3c187e	Rebranded ZX80O as ZX80O81P, with an eye to making it accept ZX81 .p files. Adjusted the initial selection part of the static analyser appropriately.	2017-06-11 21:38:32 -04:00
Thomas Harte	8116f85479	Allowed the static analyser to specify a ZX80 or 81, and a memory model. Neither is respected yet in the machine.	2017-06-11 19:12:20 -04:00
Thomas Harte	50be3a24fe	Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be.	2017-06-11 13:30:08 -04:00
Thomas Harte	7e10c7f9d8	Relocated the ZX80/81 concept of a 'file' out from Tape into Data, given that it's an exact duplicate of memory.	2017-06-08 19:09:51 -04:00
Thomas Harte	60300851ea	Started sketching out a tape parser for ZX80 and '81 files. I think this'll help me to verify whether the .O input is working.	2017-06-07 10:12:13 -04:00
Thomas Harte	8c66e1d99d	Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data.	2017-06-06 17:53:23 -04:00
Thomas Harte	cc4cb45e9d	Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court.	2017-06-06 09:25:18 -04:00
Thomas Harte	c485c460f7	Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.	2017-06-04 18:08:35 -04:00
Thomas Harte	b0a7c58287	Fixed project to point to the XIB I actually want to keep; fixed that XIB to have the correct contents.	2017-06-04 17:57:37 -04:00
Thomas Harte	d2637123c4	Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.	2017-06-04 17:55:19 -04:00
Thomas Harte	02b7c3d1b0	Added the necessary wiring to get into a ZX80/81-oriented part of the static analyser, which could in principle post a ZX80 target.	2017-06-04 17:04:06 -04:00
Thomas Harte	8c1769f157	Made a quick attempt at serialising from ZX80 .O to waves.	2017-06-04 16:59:26 -04:00
Thomas Harte	655809517c	Ensured that there is a subclass of file that is entrusted to load .O/.80 files, and that the code routes such files to it, noting that it should consider whether a ZX80 is required.	2017-06-04 16:37:03 -04:00
Thomas Harte	2190f60a89	Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.	2017-06-04 15:46:35 -04:00
Thomas Harte	0eebfdb4cc	Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.	2017-06-04 15:39:37 -04:00
Thomas Harte	7811374b0f	Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).	2017-06-04 15:07:07 -04:00