654 Commits

Author	SHA1	Message	Date
Thomas Harte	b0c2325adc	Corrected run call, and accepted that jam handling is gone forever.	2017-07-22 22:21:26 -04:00
Thomas Harte	2ff157cf7a	Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.	2017-07-22 22:17:29 -04:00
Thomas Harte	1ba3f262a2	Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.	2017-07-22 21:46:50 -04:00
Thomas Harte	6633537fb8	Discovering that there is such a thing as P81 — a ZX81 file without the name omitted — added support for it. Extended FileHolder while I was here to retain the file name and be able to supply its extension, as my quick-fix test-the-last-character approach to o/p/80/81 discrimination stops working with p81 thrown into the mix and this feels like the correct factoring.	2017-07-22 16:02:25 -04:00
Thomas Harte	2b5d0877a8	Adjusted parameter name to match documentation. I think it's a carry-over from before I was passing the whole event along.	2017-07-21 21:27:50 -04:00
Thomas Harte	2a7fc86b15	Enabled stricter warnings.	2017-07-21 20:44:35 -04:00
Thomas Harte	8f72fc4a44	Factored out from the UEF implementation the concept of being a tape that has a queue of pending pulses and manages that queue.	2017-07-16 22:04:40 -04:00
Thomas Harte	238348c885	Performed the initial wiring to announce that this application supports TZX files and to route them to the ZX80/81 static analyser. The TZX class itself does not yet do much beyond basic validation. I think it'll be easiest if it follows in UEF's footsteps in queuing up pulses ahead of time, so some factoring out is now required.	2017-07-16 21:33:11 -04:00
Thomas Harte	7b5f93510b	Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.	2017-07-16 20:55:57 -04:00
Thomas Harte	8ddd686049	Removed redundant variable.	2017-07-16 19:04:03 -04:00
Thomas Harte	2fb0aea990	Updated the C1540 test vessel to the new world.	2017-07-16 17:00:39 -04:00
Thomas Harte	279f4760d7	Eliminated buffer_size_ as something explicitly stored, and reduced size of delegate call out.	2017-07-16 15:01:39 -04:00
Thomas Harte	368bff1a82	Added a shell class that will one day be able to parse CSW files, plus the logic and metadata to instantiate it when a CSW presents itself.	2017-07-10 21:43:58 -04:00
Thomas Harte	3e5c209039	Added basic Typer support for the ZX80 and '81.	2017-07-09 22:00:34 -04:00
Thomas Harte	54efcb7e2f	Made a game attempt at automatic motor control and ensured setting is initialised correctly from the user defaults.	2017-07-08 19:31:20 -04:00
Thomas Harte	e2575d6de4	Routed tape motor selections through to the C++ side of the world, and ensured that manual tape playback works properly.	2017-07-08 19:21:12 -04:00
Thomas Harte	23e989e170	This will likely do for the Swift/XIB side of things: the play/pause button is enabled or disabled as per the user's choice of automatic tape control, and toggles function when pressed. It communicates activity down to the Objective-C[++] layer, giving it a route through to the actual machine.	2017-07-08 19:12:06 -04:00
Thomas Harte	28412150e6	Added controls for controlling the tape motor of the ZX80/81, assuming I can find an automatic option.	2017-07-08 17:59:33 -04:00
Thomas Harte	cb105fdeb4	Took a first stab at high-res support.	2017-06-22 22:48:17 -04:00
Thomas Harte	aec4fd066b	I think I've definitively decided against this model of timing.	2017-06-22 21:32:14 -04:00
Thomas Harte	95a6b0f85c	Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.	2017-06-22 21:09:26 -04:00
Thomas Harte	644ef13acd	Connected up the fast-tape GUI option for the ZX80 and '81.	2017-06-22 20:20:31 -04:00
Thomas Harte	0e0ce379b4	Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.	2017-06-21 20:38:08 -04:00
Thomas Harte	36e8a11505	Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.	2017-06-21 20:32:08 -04:00
Thomas Harte	108da64562	Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.	2017-06-20 22:25:00 -04:00
Thomas Harte	184b371649	Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.	2017-06-20 21:48:50 -04:00
Thomas Harte	27ac342928	Corrected conditional call timing, and its test.	2017-06-20 20:57:23 -04:00
Thomas Harte	6752f165db	Added failing tests for both kinds of CALL.	2017-06-19 22:03:29 -04:00
Thomas Harte	e05076b258	Added tests for everything except CALL. All passing.	2017-06-19 22:00:04 -04:00
Thomas Harte	fadbfdf801	Added DJNZ test.	2017-06-19 21:31:56 -04:00
Thomas Harte	cb277b8d1e	Added JP and JR tests.	2017-06-19 21:27:23 -04:00
Thomas Harte	234f14dbbe	Tests were at fault; all passing now.	2017-06-19 21:14:40 -04:00
Thomas Harte	99ede3a9ef	BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).	2017-06-19 21:04:14 -04:00
Thomas Harte	378233f53d	Extended to BITs and SETs, accruing three new failures.	2017-06-19 21:01:30 -04:00
Thomas Harte	f903408980	Caught up on comments.	2017-06-19 20:53:22 -04:00
Thomas Harte	b684254908	Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.	2017-06-19 20:33:34 -04:00
Thomas Harte	351d90ca55	Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.	2017-06-19 20:04:55 -04:00
Thomas Harte	23177df26a	Added various tests of the basic ALU ops.	2017-06-19 19:53:26 -04:00
Thomas Harte	ba15371948	Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.	2017-06-19 19:47:00 -04:00
Thomas Harte	8d60734737	Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.	2017-06-19 19:17:54 -04:00
Thomas Harte	002098d496	The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.	2017-06-19 07:45:41 -04:00
Thomas Harte	85c5c4405a	Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.	2017-06-19 07:30:01 -04:00
Thomas Harte	d668879ba6	Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.	2017-06-18 22:03:13 -04:00
Thomas Harte	e1a2580b2a	Renamed BusOperation to MachineCycle::Operation.	2017-06-17 21:53:45 -04:00
Thomas Harte	b6f51474ff	Ensured that -description can handle the newly-captured bus actions.	2017-06-17 18:20:30 -04:00
Thomas Harte	0f18768091	Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.	2017-06-17 18:19:25 -04:00
Thomas Harte	50cd617bd9	Ensured test raises only the intentional failure exceptions.	2017-06-15 22:33:46 -04:00
Thomas Harte	838b818cd3	Finished transcribing first page of machine cycle documentation; several failures contained.	2017-06-15 22:19:49 -04:00
Thomas Harte	cf795562bf	Continued filling in tests, fleshing out what the test machine captures as a result.	2017-06-15 20:59:59 -04:00
Thomas Harte	ac37424878	Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.	2017-06-15 19:06:59 -04:00