Thomas Harte
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d910a4fd38
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Adjusted to signal an interrupt during the refresh cycle rather than weirdly just afterwards. Which cuts video timing down by 4 cycles a line. There still might be a problem here somewhere though, as I'm getting 206 cycles/line and the internet states it should be 207.
Also: lots of printfs have grown temporarily as I try to figure out what I'm doing so wrong as to break loading.
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2017-06-11 13:32:20 -04:00 |
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Thomas Harte
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5626d35bc4
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Tried flipping the bit meaning; decided at least to leave it in full-byte form.
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2017-06-06 18:38:05 -04:00 |
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Thomas Harte
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63e0802f4e
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Ensured tape input appears on the returned value.
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2017-06-06 18:16:27 -04:00 |
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Thomas Harte
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e3ee9604a5
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Added comments.
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2017-06-06 18:01:33 -04:00 |
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Thomas Harte
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8c66e1d99d
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Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data.
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2017-06-06 17:53:23 -04:00 |
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Thomas Harte
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ca9e8aecd6
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Made a seemingly unsuccessful attempt to add tape input.
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2017-06-06 10:13:32 -04:00 |
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Thomas Harte
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cc4cb45e9d
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Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court.
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2017-06-06 09:25:18 -04:00 |
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Thomas Harte
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ebbf6e6133
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Surprisingly, I think this may actually be the correct output: stopped throwing away the I part of the refresh register and flipped black and white.
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2017-06-06 09:03:09 -04:00 |
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Thomas Harte
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cba07dec7e
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Doubled up to display all eight pixels. To confirm that they are the wrong pixels.
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2017-06-06 08:59:00 -04:00 |
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Thomas Harte
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6f7037b2b1
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Made an initial stab at outputting half the correct pixels.
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2017-06-06 08:55:07 -04:00 |
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Thomas Harte
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ef4b2f963d
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Probably more-or-less corrected. But this is all a bit too interdependent.
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2017-06-05 23:52:56 -04:00 |
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Thomas Harte
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97f3ff03b6
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Restored white background and attempted to correct output timing deficiencies. Incomplete success.
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2017-06-05 23:50:04 -04:00 |
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Thomas Harte
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2fbc7a2869
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Made a very basic attempt at getting something that at least demarcates proper graphics output.
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2017-06-05 23:32:49 -04:00 |
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Thomas Harte
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4983718df7
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Got to outputting something to the CRT. Should be just proper syncs and a paper background. It's not synchronising properly, so something is amiss in my timing.
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2017-06-05 10:47:42 -04:00 |
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Thomas Harte
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23ca00fd9a
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Added memory fuzzing as a way to verify state being written by the Z80. Eventually discovered the HALT problem as fixed in the last commit, so have stripped away the caveman stuff again.
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2017-06-05 10:36:07 -04:00 |
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Thomas Harte
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893f61b490
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Attempted specifically to reproduce the 1kb ZX80 memory map in the hope of getting compact lines and in case mirroring is why I'm getting completely empty video reads. Still no action.
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2017-06-05 09:38:49 -04:00 |
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Thomas Harte
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7e3a46c33e
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[Re]discovered that sync may also be a product of the interrupt cycle. So started looking into that.
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2017-06-04 21:54:55 -04:00 |
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Thomas Harte
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73654d51dd
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Wired up actually to run.
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2017-06-04 18:37:13 -04:00 |
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Thomas Harte
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096551ab3e
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Made a first attempt to hash out the ZX80's bus. Video output isn't yet going though. Can't seem to find clarity on whether horizontal sync is really programmatic. Let's see.
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2017-06-04 18:32:23 -04:00 |
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Thomas Harte
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c485c460f7
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Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.
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2017-06-04 18:08:35 -04:00 |
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Thomas Harte
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d2637123c4
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Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.
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2017-06-04 17:55:19 -04:00 |
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