Thomas Harte
e650f3772a
Limit vertical visibility.
2024-09-30 13:35:28 -04:00
Thomas Harte
e5ff4c65b7
Fix accidental skew, off-by-one end of line.
2024-09-30 13:20:18 -04:00
Thomas Harte
276809f76a
Stabilise image, albeit incorrectly.
2024-09-30 13:16:03 -04:00
Thomas Harte
5e3840c5f1
Attempt to skirt with coherence.
2024-09-29 23:08:39 -04:00
Thomas Harte
6eace2a3ef
Improve address counting.
2024-09-27 21:27:56 -04:00
Thomas Harte
7817b23857
Take a swing at vertical sync.
2024-09-27 21:14:57 -04:00
Thomas Harte
432854aeb5
Restore some form of visuals.
2024-09-26 22:08:22 -04:00
Thomas Harte
433c8f9c3c
Make negligible progress.
2024-09-25 19:30:08 -04:00
Thomas Harte
ea25dbfd1e
Begin CRTC rejig.
2024-09-23 21:11:54 -04:00
Thomas Harte
43887b42b1
Allow vsync on line 0.
2024-08-07 23:05:26 -04:00
Thomas Harte
a3d37640aa
Switch include guards to #pragma once.
2024-01-16 23:34:46 -05:00
Thomas Harte
42731be11f
Remove non-functional EGA switches.
2024-01-11 22:00:48 -05:00
Thomas Harte
e919386c79
Grab cursor type.
2024-01-11 15:10:43 -05:00
Thomas Harte
22b4b4d4e3
Switch to named values for everything except blink mode.
2024-01-09 22:03:24 -05:00
Thomas Harte
5f00d29297
Subsume vertical sync position.
2024-01-08 22:28:46 -05:00
Thomas Harte
f1453d9363
Introduce some vertical metrics.
2024-01-08 21:49:24 -05:00
Thomas Harte
8290220657
Begin process of meaningful naming.
...
This is in part for readability, but primarily because the differences in VGA/EGA register definitions are better handled at set rather than during execution.
2024-01-08 15:35:44 -05:00
Thomas Harte
8c0ac6158c
Adjust indentation.
2024-01-01 22:45:11 -05:00
Thomas Harte
99351ee2de
Extend refresh address to 16-bit in 'EGA' mode.
2023-12-27 16:17:25 -05:00
Thomas Harte
a617f7305a
Move personality into type.
2023-12-27 16:15:52 -05:00
Thomas Harte
9601c69e12
Implement blinking text.
2023-12-04 22:02:38 -05:00
Thomas Harte
8103f8e682
Switch interpretation to support cursor on/off.
2023-12-04 15:54:56 -05:00
Thomas Harte
646c6b08f7
Make cursor blink.
2023-12-04 09:52:46 -05:00
Thomas Harte
0d7646d42a
Add a cursor-type template parameter.
2023-12-04 09:45:32 -05:00
Thomas Harte
5d8666b837
Enable the cursor signal; no blink action yet.
2023-12-03 17:57:19 -05:00
Thomas Harte
2b56b7be0d
Simplify namespace syntax.
2023-05-10 16:02:18 -05:00
Thomas Harte
25996ce180
Further doubles down on construction syntax for type conversions.
2020-05-09 23:00:39 -04:00
Thomas Harte
1c154131f9
Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.
2019-10-29 22:36:29 -04:00
Thomas Harte
5d6b5d9f10
Eliminates all emdashes in cross-platform code.
2018-05-13 15:34:31 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
3944e734d3
Ensures full 6845 instance state initialisation and uses an unsigned shifter.
2017-10-17 22:10:28 -04:00
Thomas Harte
edb9fd301c
Begins this project's conversion to functional-style casts.
2017-10-03 22:04:15 -04:00
Thomas Harte
b30bb2a234
Adds an initial implementation of display skew, as a completely live property.
2017-08-29 22:16:40 -04:00
Thomas Harte
334afbc710
Removes const from get_status and get_register, as both may now logically mutate the object.
2017-08-27 18:13:55 -04:00
Thomas Harte
17c13624e5
Improved comments.
2017-08-27 18:11:40 -04:00
Thomas Harte
113349d272
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 18:10:07 -04:00
Thomas Harte
bdda701207
Reverts previous unevidenced change.
2017-08-26 22:58:16 -04:00
Thomas Harte
487fe83dca
Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.
2017-08-26 17:54:54 -04:00
Thomas Harte
6c5a03187b
Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test.
2017-08-26 17:22:48 -04:00
Thomas Harte
7d7aa2f5d5
Eliminates repetition of the unpacking of register 3 into a horizontal sync count.
2017-08-26 14:37:03 -04:00
Thomas Harte
28550c0227
Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
2017-08-26 13:56:23 -04:00
Thomas Harte
6e99169348
Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
2017-08-26 12:59:59 -04:00
Thomas Harte
3caa4705ca
Limits sync counter size.
2017-08-26 12:31:19 -04:00
Thomas Harte
039aed1bd1
Switches the two sync counters to upward-going rather than downward, as a more likely match to the way the rest of the 6845 implementation.
2017-08-25 21:26:01 -04:00
Thomas Harte
a914eadc85
Ensured that register 6 is checked on every loop.
2017-08-22 22:17:45 -04:00
Thomas Harte
e956740c56
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-22 21:54:48 -04:00
Thomas Harte
55055c7847
Minor: ensured immediate line comparison works. But I think my problem might be trying to do this as straight line logic?
2017-08-14 19:08:20 -04:00
Thomas Harte
a10389a22c
Factored out the stuff of stuffing the bus.
2017-08-14 12:42:22 -04:00
Thomas Harte
a5593bec79
Threw in support for the light-pen trigger.
2017-08-10 15:00:14 -04:00
Thomas Harte
a1e2646301
Imposed counter size limits.
2017-08-10 14:58:24 -04:00
