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11,522 Commits 8 Branches 121 Tags 496 MiB
ea6b83815b
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1368 Commits

Author SHA1 Message Date
Thomas Harte
ea6b83815b Add a further category of exclusions. 2024-03-28 14:01:37 -04:00
Thomas Harte
740b0e35d5 Completely bypass ignored tests. 2024-03-28 11:28:37 -04:00
Thomas Harte
4fcb85d132 Cleave off most remaining reasons for failure. 2024-03-28 10:32:27 -04:00
Thomas Harte
c04c708a9d Trade some depth for breadth. 2024-03-27 22:37:10 -04:00
Thomas Harte
f4cf1e5313 Attempt to cleave by broad reason. 2024-03-27 22:36:37 -04:00
Thomas Harte
3549488b7a Add round-trip test for status flags. 2024-03-24 22:18:16 -04:00
Thomas Harte
2ad6bb099b Begin foray into disassembly. 2024-03-19 11:34:10 -04:00
Thomas Harte
3a899ea4be Add test coverage for STM descending, proving nothing. 2024-03-15 14:55:17 -04:00
Thomas Harte
e7457461ba Reduce magic constants. 2024-03-11 14:49:03 -04:00
Thomas Harte
ca779bc841 Expand test set. 2024-03-11 14:48:18 -04:00
Thomas Harte
db49146efe Figure out what's going on with TEQ. 2024-03-11 09:51:09 -04:00
Thomas Harte
830d70d3aa Trust tests on immediate-opcode ROR 0; limit shift by register. 2024-03-10 23:38:31 -04:00
Thomas Harte
336292bc49 Further correct R15 as a destination. 2024-03-10 22:56:02 -04:00
Thomas Harte
bd62228cc6 The test set doesn't seem to do word rotation. 2024-03-10 22:40:37 -04:00
Thomas Harte
ccdd340c9a Reads also may or may not be aligned. *sigh* 2024-03-10 22:34:56 -04:00
Thomas Harte
0b42f5fb30 Make further test-set allowances. 2024-03-10 22:29:40 -04:00
Thomas Harte
21278d028c Correct unaligned accesses. 2024-03-10 21:56:19 -04:00
Thomas Harte
fbc273f114 Add invented model for tests. 2024-03-10 21:45:56 -04:00
Thomas Harte
06a5df029d Summarise failures. 2024-03-10 16:56:39 -04:00
Thomas Harte
e17700b495 Permit digression for 03110002, temporarily. 2024-03-10 14:47:02 -04:00
Thomas Harte
655b1e516c Test PSR and PC. 2024-03-10 14:14:18 -04:00
Thomas Harte
4e7a63f792 Do a de minimis checking of memory accesses. 2024-03-09 15:18:35 -05:00
Thomas Harte
a2896b9bd0 Test register values. 2024-03-09 15:11:12 -05:00
Thomas Harte
d6f882a8bb Integrate PC and PSR, guarantee invisible register values. 2024-03-09 14:59:44 -05:00
Thomas Harte
08f50f3eff Box in flags. 2024-03-08 23:01:29 -05:00
Thomas Harte
47f7340dfc Start hacking in some ARM tests. 2024-03-08 22:54:42 -05:00
Thomas Harte
9406a97141 Add some register switch tests. 2024-03-08 11:34:10 -05:00
Thomas Harte
0d666f9935 Get a bit more rigorous about reporting. 2024-03-06 09:54:39 -05:00
Thomas Harte
230e9c6327 Obscure active. 2024-03-03 21:43:30 -05:00
Thomas Harte
11c4d2f09e Add further exposition. 2024-03-03 21:38:27 -05:00
Thomas Harte
b42a6e447d Tie down more corners. 2024-03-03 21:29:53 -05:00
Thomas Harte
4e7963ee81 Clarify PC semantics; remove faulty underscore. 2024-03-03 14:11:02 -05:00
Thomas Harte
945b7e90da Add just enough to persuade self that execution is broadly sane. 2024-03-03 14:03:08 -05:00
Thomas Harte
99f0233b76 Fix immediate offset and data processing operation. 2024-03-02 23:27:37 -05:00
Thomas Harte
62da0dee7f Unify reads. 2024-03-02 23:15:17 -05:00
Thomas Harte
1663d3d9d1 Introduce disaster of an attempted test run. 2024-03-02 22:40:12 -05:00
Thomas Harte
c0dd96eb7c Add a catalogue entry for RISC OS. 2024-03-02 21:44:27 -05:00
Thomas Harte
c865da67e0 Introduce further barrel-shifter tests. 2024-03-02 15:12:03 -05:00
Thomas Harte
e6f77a9b80 Add logical right-shift tests. 2024-03-01 18:06:54 -05:00
Thomas Harte
42ba6d1281 Relocate execution code appropriately. 2024-03-01 15:02:47 -05:00
Thomas Harte
85b7afd530 Attempt a complete block data transfer. 2024-03-01 14:48:36 -05:00
Thomas Harte
f2f59a4de5 Attempt to deal with data aborts. 2024-03-01 10:38:08 -05:00
Thomas Harte
5759798ad7 Deal with downward write order. 2024-02-29 14:34:20 -05:00
Thomas Harte
ab1dd7f57e Implement a little of block data transfer. 2024-02-29 11:33:40 -05:00
Thomas Harte
53a2ea3a57 Add address exception. 2024-02-29 10:49:11 -05:00
Thomas Harte
1f1e7236be Add rotation. 2024-02-29 10:47:41 -05:00
Thomas Harte
fd2c5b6679 Make a quick first attempt at memory accesses. 2024-02-29 10:18:09 -05:00
Thomas Harte
0b287c55d5 Edge towards single data transfer. 2024-02-29 10:02:57 -05:00
Thomas Harte
93b4008f81 Localise flags, detect improper carry write. 2024-02-28 21:28:19 -05:00
Thomas Harte
904462b881 Regularise data transfers. 2024-02-28 21:23:57 -05:00