12 Commits

Author	SHA1	Message	Date
Thomas Harte	7cb82fccc0	Attempts properly to maintain interrupt flag; adds delegate.	2019-10-21 22:40:38 -04:00
Thomas Harte	83f5f0e2ad	Begins trying to receive ACIA data.	2019-10-21 20:10:19 -04:00
Thomas Harte	4134463094	The ACIA now receives bits.	2019-10-20 23:34:30 -04:00
Thomas Harte	cf07982a9b	Ensures good serial line and ACIA behaviour. ... Next stop: having the intelligent keyboard react.	2019-10-20 22:10:05 -04:00
Thomas Harte	c10b64e1c0	Adds a received_data_ register, that presently can never fill.	2019-10-20 20:38:55 -04:00
Thomas Harte	ff62eb6dce	The ACIA actually has two clocks, though on an ST they're both 500,000 Hz.	2019-10-20 20:38:55 -04:00
Thomas Harte	374439693e	Ensures serial lines know their writer's clock rate.	2019-10-20 20:38:55 -04:00
Thomas Harte	a7ed357569	Attempts to implement transmission interrupts and ClockingHint::Source.	2019-10-20 20:38:55 -04:00
Thomas Harte	4e5b440145	Attempts mostly to implement 6850 output.	2019-10-20 20:38:55 -04:00
Thomas Harte	2bd7be13b5	Decodes the 6850 control register, and starts working on standardised serial ports.	2019-10-20 20:38:55 -04:00
Thomas Harte	4b09d7c41d	Nudges 6850 towards coherence.	2019-10-20 20:38:55 -04:00
Thomas Harte	4ead905c3c	Adds an empty shell for the ACIA.	2019-10-20 20:38:55 -04:00