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320 lines
9.1 KiB
C++
320 lines
9.1 KiB
C++
//
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// Video.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/12/2016.
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// Copyright 2016 Thomas Harte. All rights reserved.
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//
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#include "Video.hpp"
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#include <cstring>
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using namespace Electron;
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// MARK: - Lifecycle
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VideoOutput::VideoOutput(const uint8_t *memory) :
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ram_(memory),
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crt_(h_total,
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1,
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Outputs::Display::Type::PAL50,
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Outputs::Display::InputDataType::Red1Green1Blue1) {
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// Default construction values leave this out of text mode, and text
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// mode uses a subregion of pixel modes.
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crt_.set_fixed_framing([&] {
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run_for(Cycles(10'000));
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});
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}
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void VideoOutput::set_scan_target(Outputs::Display::ScanTarget *const scan_target) {
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crt_.set_scan_target(scan_target);
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}
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Outputs::Display::ScanStatus VideoOutput::get_scaled_scan_status() const {
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return crt_.get_scaled_scan_status();
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}
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void VideoOutput::set_display_type(const Outputs::Display::DisplayType display_type) {
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crt_.set_display_type(display_type);
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}
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Outputs::Display::DisplayType VideoOutput::get_display_type() const {
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return crt_.get_display_type();
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}
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// The below is my attempt at transcription of the equivalent VHDL code in moogway82's
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// JamSoftElectronULA — https://github.com/moogway82/JamSoftElectronULA — which is itself
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// derived from hoglet67's https://github.com/hoglet67/ElectronFpga and that author's
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// reverse-engineering of the Electron ULA. It should therefore be as accurate to the
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// original hardware as my comprehension of VHDL and adaptation into sequential code allows.
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uint8_t VideoOutput::perform(const int h_count, const int v_count) {
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uint8_t interrupts{};
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// In this, the sequential world of C++, all tests below should assume that the position
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// named by (h_count, v_count) is the one that was active **prior to this cycle**.
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//
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// So this cycle spans the period from (h_count, v_count) to (h_count, v_count)+1.
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// Update syncs.
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if(!field_) {
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if(!h_count && v_count == vsync_start) {
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vsync_int_ = true;
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} else if(h_count == h_half && v_count == vsync_end) {
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vsync_int_ = false;
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}
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} else {
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if(h_count == h_half && v_count == vsync_start) {
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vsync_int_ = true;
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} else if(!h_count && v_count == vsync_end + 1) {
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vsync_int_ = false;
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}
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}
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if(h_count == hsync_start) {
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hsync_int_ = true;
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} else if(h_count == hsync_end) {
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hsync_int_ = false;
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}
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// Update character row on the trailing edge of hsync.
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if(h_count == hsync_end) {
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if(is_v_end()) {
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char_row_ = 0;
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} else {
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char_row_ = last_line() ? 0 : char_row_ + 1;
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}
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}
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// Disable the top bit of the char_row counter outside of text mode.
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if(!mode_text_) {
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char_row_ &= 7;
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}
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// Latch video address at frame start.
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if(h_count == h_reset_addr && is_v_end()) {
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row_addr_ = byte_addr_ = screen_base_;
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}
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// Copy byte_addr back into row_addr if a new character row has begun.
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if(hsync_int_) {
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if(last_line()) {
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row_addr_ = byte_addr_;
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} else {
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byte_addr_ = row_addr_;
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}
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}
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// Determine current output item.
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OutputStage stage;
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int screen_pitch = screen_pitch_;
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if(vsync_int_ || hsync_int_) {
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stage = OutputStage::Sync;
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} else if(in_blank()) {
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if(h_count >= hburst_start && h_count < hburst_end) {
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stage = OutputStage::ColourBurst;
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} else {
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stage = OutputStage::Blank;
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}
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} else {
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stage = OutputStage::Pixels;
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screen_pitch = (mode_40_ ? 320 : 640) / static_cast<int>(mode_bpp_);
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}
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if(stage != output_ || screen_pitch != screen_pitch_) {
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switch(output_) {
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case OutputStage::Sync: crt_.output_sync(output_length_); break;
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case OutputStage::Blank: crt_.output_blank(output_length_); break;
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case OutputStage::ColourBurst: crt_.output_default_colour_burst(output_length_); break;
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case OutputStage::Pixels:
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if(current_output_target_) {
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crt_.output_data(
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output_length_,
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static_cast<size_t>(current_output_target_ - initial_output_target_)
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);
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} else {
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crt_.output_data(output_length_);
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}
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break;
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}
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output_length_ = 0;
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output_ = stage;
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screen_pitch_ = screen_pitch;
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if(stage == OutputStage::Pixels) {
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initial_output_target_ = current_output_target_ = crt_.begin_data(static_cast<size_t>(screen_pitch_));
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}
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}
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output_length_ += 8;
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if(output_ == OutputStage::Pixels && (!mode_40_ || h_count & 8) && current_output_target_) {
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const uint8_t data = ram_[byte_addr_ | char_row_];
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switch(mode_bpp_) {
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case Bpp::One:
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// Maps 1bpp to 4bpp as:
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//
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// 0 -> 0000
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// 1 -> 1000
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current_output_target_[0] = mapped_palette_[(data >> 4) & 8];
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current_output_target_[1] = mapped_palette_[(data >> 3) & 8];
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current_output_target_[2] = mapped_palette_[(data >> 2) & 8];
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current_output_target_[3] = mapped_palette_[(data >> 1) & 8];
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current_output_target_[4] = mapped_palette_[(data >> 0) & 8];
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current_output_target_[5] = mapped_palette_[(data << 1) & 8];
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current_output_target_[6] = mapped_palette_[(data << 2) & 8];
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current_output_target_[7] = mapped_palette_[(data << 3) & 8];
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current_output_target_ += 8;
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break;
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case Bpp::Two:
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// Maps 2bpp to 4bpp as:
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//
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// 00 -> 0000
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// 01 -> 1000
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// 10 -> 0010
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// 11 -> 1010
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current_output_target_[0] = mapped_palette_[((data >> 4) & 8) | ((data >> 2) & 2)];
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current_output_target_[1] = mapped_palette_[((data >> 3) & 8) | ((data >> 1) & 2)];
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current_output_target_[2] = mapped_palette_[((data >> 2) & 8) | ((data >> 0) & 2)];
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current_output_target_[3] = mapped_palette_[((data >> 1) & 8) | ((data << 1) & 2)];
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current_output_target_ += 4;
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break;
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case Bpp::Four:
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current_output_target_[0] =
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mapped_palette_[((data >> 4) & 8) | ((data >> 3) & 4) | ((data >> 2) & 2) | ((data >> 1) & 1)];
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current_output_target_[1] =
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mapped_palette_[((data >> 3) & 8) | ((data >> 2) & 4) | ((data >> 1) & 2) | ((data >> 0) & 1)];
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current_output_target_ += 2;
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break;
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}
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}
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// Increment the byte address across the line.
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// (slghtly pained logic here because the input clock is at the pixel rate, not the byte rate)
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if(h_count < h_active) {
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if(
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(!mode_40_ && !(h_count & 0x7)) ||
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(mode_40_ && ((h_count & 0xf) == 0x8))
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) {
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byte_addr_ += 8;
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if(!(byte_addr_ & 0b0111'1000'0000'0000)) {
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byte_addr_ = mode_base_ | (byte_addr_ & 0x0000'0111'1111'1111);
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}
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}
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}
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// Test for interrupts.
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if(v_count == v_rtc && ((!field_ && !h_count) || (field_ && h_count == h_half))) {
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interrupts |= static_cast<uint8_t>(Interrupt::RealTimeClock);
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}
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if(h_count == hsync_start && ((v_count == v_disp_gph && !mode_text_) or (v_count == v_disp_txt && mode_text_))) {
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interrupts |= static_cast<uint8_t>(Interrupt::DisplayEnd);
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}
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return interrupts;
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}
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uint8_t VideoOutput::run_for(const Cycles cycles) {
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uint8_t interrupts{};
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int number_of_cycles = cycles.as<int>();
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while(number_of_cycles--) {
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interrupts |= perform(h_count_, v_count_);
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// Horizontal and vertical counter updates.
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h_count_ += 8;
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if(h_count_ == h_total) {
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h_count_ = 0;
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if(is_v_end()) {
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v_count_ = 0;
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field_ = !field_;
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} else {
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++v_count_;
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}
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}
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}
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return interrupts;
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}
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std::pair<Cycles, uint8_t> VideoOutput::run_until_ram_slot() {
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if(mode_40_) {
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return run_until_io_slot();
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}
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Cycles duration{};
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uint8_t interrupts{};
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// If currently in the back half of a cycle,
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// advance to the start of the next 1Mhz window.
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if(h_count_ & 8) {
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duration += Cycles(1);
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interrupts |= run_for(Cycles(1));
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}
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// If now in blank, just finish out the half window.
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// Otherwise let the pixel run end.
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if(!in_blank()) {
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const auto additional = Cycles(1 + ((h_active - h_count_) >> 3));
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duration += additional;
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interrupts |= run_for(additional);
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} else {
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duration += Cycles(1);
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interrupts |= run_for(Cycles(1));
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}
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return std::make_pair(duration, interrupts);
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}
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std::pair<Cycles, uint8_t> VideoOutput::run_until_io_slot() {
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// Two cycles minimum are required; ensure also that the next access
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// ends at the midpoint of a 1Mhz window. In each window the CPU
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// access conceptually comes first.
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const auto duration = 3 - ((h_count_ >> 3) & 1);
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return std::make_pair(duration, run_for(duration));
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}
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// MARK: - Register hub
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void VideoOutput::write(const int address, const uint8_t value) {
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switch(address & 0b1111) {
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case 0x02:
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screen_base_ =
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(screen_base_ & 0b0111'1110'0000'0000) |
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((value << 1) & 0b0000'0001'1100'0000);
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break;
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case 0x03:
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screen_base_ =
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((value << 9) & 0b0111'1110'0000'0000) |
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(screen_base_ & 0b0000'0001'1100'0000);
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break;
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case 0x07: {
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const uint8_t mode = (value >> 3) & 7;
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mode_40_ = mode >= 4;
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mode_text_ = mode == 3 || mode == 6;
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switch(mode) {
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case 0:
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case 1:
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case 2: mode_base_ = 0x3000; break;
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case 3: mode_base_ = 0x4000; break;
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case 6: mode_base_ = 0x6000; break;
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default: mode_base_ = 0x5800; break;
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}
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switch(mode) {
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default: mode_bpp_ = Bpp::One; break;
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case 1:
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case 5: mode_bpp_ = Bpp::Two; break;
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case 2: mode_bpp_ = Bpp::Four; break;
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}
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} break;
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case 0x08: case 0x09: set_palette_group<0xfe08, 0b0000>(address, value); break;
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case 0x0a: case 0x0b: set_palette_group<0xfe0a, 0b0100>(address, value); break;
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case 0x0c: case 0x0d: set_palette_group<0xfe0c, 0b0101>(address, value); break;
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case 0x0e: case 0x0f: set_palette_group<0xfe0e, 0b0001>(address, value); break;
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}
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}
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