This website requires JavaScript.
Explore
Mirrors
Help
Sign In
6502
/
CLK
Watch
1
Star
0
Fork
0
You've already forked CLK
mirror of
https://github.com/TomHarte/CLK.git
synced
2024-11-26 23:52:26 +00:00
Code
Issues
Projects
Releases
Wiki
Activity
1c9a744b01
CLK
/
Components
History
Thomas Harte
1c9a744b01
Made an effort to start inspecting ID fields, at least. Discovered that my emulation has somehow stopped proceeding beyond sense interrupt status though. Fix one in that area: adjust ST0 just in time for the sense interrupt status response, as that'll need to specify the drive number properly.
2017-08-06 18:06:20 -04:00
..
1770
Fixed WAIT_FOR_TIME macro.
2017-08-06 12:08:54 -04:00
6522
6532
6560
6845
Permitted register 3 to dictate vertical sync length.
2017-08-04 08:56:36 -04:00
8255
8272
Made an effort to start inspecting ID fields, at least. Discovered that my emulation has somehow stopped proceeding beyond sense interrupt status though. Fix one in that area: adjust ST0 just in time for the sense interrupt status response, as that'll need to specify the drive number properly.
2017-08-06 18:06:20 -04:00
AY38910
Attempted to move to more accurate bus reading — if control lines are set then all subsequent data inputs should act according to the current control lines; changes to port input should be reflected live upon readings, etc.
2017-08-02 19:45:58 -04:00