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https://github.com/TomHarte/CLK.git
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5ccb512883
This reflects the routing of interrupt signals for now, but also prepares for the addition of disk drives.
82 lines
2.4 KiB
C++
82 lines
2.4 KiB
C++
//
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// MemoryMap.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 04/10/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef MemoryMap_hpp
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#define MemoryMap_hpp
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namespace Amiga {
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struct MemoryMap {
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public:
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std::array<uint8_t, 512*1024> chip_ram{};
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std::array<uint8_t, 512*1024> kickstart{0xff};
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struct MemoryRegion {
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uint8_t *contents = nullptr;
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unsigned int read_write_mask = 0;
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} regions[64]; // i.e. top six bits are used as an index.
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MemoryMap() {
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// Address spaces that matter:
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//
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// 00'0000 – 08'0000: chip RAM. [or overlayed KickStart]
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// – 10'0000: extended chip ram for ECS.
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// – 20'0000: auto-config space (/fast RAM).
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// ...
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// bf'd000 – c0'0000: 8250s.
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// c0'0000 – d8'0000: pseudo-fast RAM.
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// ...
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// dc'0000 – dd'0000: optional real-time clock.
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// df'f000 - e0'0000: custom chip registers.
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// ...
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// f0'0000 — : 512kb Kickstart (or possibly just an extra 512kb reserved for hypothetical 1mb Kickstart?).
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// f8'0000 — : 256kb Kickstart if 2.04 or higher.
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// fc'0000 – : 256kb Kickstart otherwise.
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set_region(0xfc'0000, 0x1'00'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
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reset();
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}
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void reset() {
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set_overlay(true);
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}
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void set_overlay(bool enabled) {
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if(overlay_ == enabled) {
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return;
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}
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overlay_ = enabled;
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if(enabled) {
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set_region(0x00'0000, 0x08'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
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} else {
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// Mirror RAM to fill out the address range up to $20'0000.
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set_region(0x00'0000, 0x08'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x08'0000, 0x10'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x10'0000, 0x18'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x18'0000, 0x20'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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}
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}
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private:
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bool overlay_ = false;
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void set_region(int start, int end, uint8_t *base, unsigned int read_write_mask) {
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assert(!(start & ~0xfc'0000));
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assert(!((end - (1 << 18)) & ~0xfc'0000));
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base -= start;
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for(int c = start >> 18; c < end >> 18; c++) {
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regions[c].contents = base;
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regions[c].read_write_mask = read_write_mask;
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}
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}
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};
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}
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#endif /* MemoryMap_hpp */
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