mirror of
https://github.com/TomHarte/CLK.git
synced 2024-11-27 15:50:56 +00:00
558 lines
22 KiB
Plaintext
558 lines
22 KiB
Plaintext
//===============
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// SNES Graphics
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//===============
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//=============================
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// WaitNMI - Wait For NMI Flag
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//=============================
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macro WaitNMI() {
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-
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bit.w REG_RDNMI // $4210: Read NMI Flag Register
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bpl - // Wait For NMI Flag
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}
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//======================================
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// WaitHV - Wait For H/V Timer IRQ Flag
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//======================================
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macro WaitHV() {
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-
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bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag
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bpl - // Wait For H/V Timer IRQ Flag
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}
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//========================================
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// WaitHVB - Wait For V-Blank Period Flag
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//========================================
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macro WaitHVB() {
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-
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bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
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bpl - // Wait For V-Blank Period Flag
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}
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//================================================================
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// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing)
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//================================================================
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macro FadeIN() {
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ldx.w #$0000 // Set X To Mininmum Brightness Level
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-
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bit.w REG_RDNMI // $4210: Read NMI Flag Register
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bpl - // Wait For NMI Flag
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inx // Increments Brightness Level
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txa // Swap 16-Bit X To 8-Bit A
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sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
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cmp.b #$0F // Compare With Maximum Brightness Level (15)
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bne - // IF (Screen != Maximum Brightness Level) Loop
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}
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//=================================================================
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// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing)
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//=================================================================
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macro FadeOUT() {
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ldx.w #$000F // Set X To Maximum Brightness Level
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-
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bit.w REG_RDNMI // $4210: Read NMI Flag Register
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bpl - // Wait For NMI Flag
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dex // Decrement Brightness Level
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txa // Swap 16-Bit X To 8-Bit A
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sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
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cmp.b #$00 // Compare With Minimum Brightness Level
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bne - // IF (Screen != Minimum Brightness Level) Loop
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}
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//======================================
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// LoadPAL - Load Palette Data To CGRAM
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//======================================
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// SRC: 24-Bit Address Of Source Data
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// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
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// SIZE: Size Of Data (# Of Colors To Copy)
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro LoadPAL(SRC, DEST, SIZE, CHAN) {
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lda.b #{DEST} // Set CGRAM Destination
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sta.w REG_CGADD // $2121: CGRAM
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stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
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lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRC} // Set Source Offset
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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lda.b #{SRC} >> 16 // Set Source Bank
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sta.w REG_A1B{CHAN} // $43X4: Source Bank
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ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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}
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//==========================================
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// UpdatePAL - Update Palette Data To CGRAM
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//==========================================
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// SRC: 24-Bit Address Of Source Data
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// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
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// SIZE: Size Of Data (# Of Colors To Copy)
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro UpdatePAL(SRC, DEST, SIZE, CHAN) {
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lda.b #{DEST} // Set CGRAM Destination
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sta.w REG_CGADD // $2121: CGRAM
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stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
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lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRC} // Set Source Offset
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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lda.b #{SRC} >> 16 // Set Source Bank
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sta.w REG_A1B{CHAN} // $43X4: Source Bank
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ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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-
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bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
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bpl - // Wait For V-Blank Period Flag
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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}
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//========================================
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// ClearLOVRAM - Clear VRAM Lo Fixed Byte
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//========================================
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// SRC: 24-Bit Address Of Source Data
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// DEST: 16-Bit VRAM Destination (WORD Address)
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// SIZE: Size Of Data (BYTE Size)
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) {
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stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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stx.w REG_VMADDL // $2116: VRAM
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lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
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sta.w REG_DMAP{CHAN} // $43X0: DMA Control
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lda.b #$18 // Set Destination Register ($2118: VRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRC} // Set Source Offset (Lo Byte)
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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lda.b #{SRC} >> 16 // Set Source Bank
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sta.w REG_A1B{CHAN} // $43X4: Source Bank
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ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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}
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//========================================
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// ClearHIVRAM - Clear VRAM Hi Fixed Byte
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//========================================
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// SRC: 24-Bit Address Of Source Data
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// DEST: 16-Bit VRAM Destination (WORD Address)
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// SIZE: Size Of Data (BYTE Size)
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) {
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lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
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sta.w REG_VMAIN // $2115: Video Port Control
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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stx.w REG_VMADDL // $2116: VRAM
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lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
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sta.w REG_DMAP{CHAN} // $43X0: DMA Control
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lda.b #$19 // Set Destination Register ($2119: VRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRC} // Set Source Offset (Lo Byte)
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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lda.b #{SRC} >> 16 // Set Source Bank
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sta.w REG_A1B{CHAN} // $43X4: Source Bank
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ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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}
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//===================================
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// ClearVRAM - Clear VRAM Fixed Word
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//===================================
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// SRC: 24-Bit Address Of Source Data
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// DEST: 16-Bit VRAM Destination (WORD Address)
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// SIZE: Size Of Data (BYTE Size)
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro ClearVRAM(SRC, DEST, SIZE, CHAN) {
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// Transfer Lo Byte
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stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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stx.w REG_VMADDL // $2116: VRAM
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lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
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sta.w REG_DMAP{CHAN} // $43X0: DMA Control
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lda.b #$18 // Set Destination Register ($2118: VRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRC} // Set Source Offset (Lo Byte)
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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lda.b #{SRC} >> 16 // Set Source Bank
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sta.w REG_A1B{CHAN} // $43X4: Source Bank
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ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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// Transfer Hi Byte
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lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
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sta.w REG_VMAIN // $2115: Video Port Control
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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stx.w REG_VMADDL // $2116: VRAM
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lda.b #$19 // Set Destination Register ($2119: VRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte)
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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}
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//==================================
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// LoadVRAM - Load GFX Data To VRAM
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//==================================
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// SRC: 24-Bit Address Of Source Data
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// DEST: 16-Bit VRAM Destination (WORD Address)
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// SIZE: Size Of Data (BYTE Size)
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro LoadVRAM(SRC, DEST, SIZE, CHAN) {
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lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
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sta.w REG_VMAIN // $2115: Video Port Control
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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stx.w REG_VMADDL // $2116: VRAM
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lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
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sta.w REG_DMAP{CHAN} // $43X0: DMA Control
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lda.b #$18 // Set Destination Register ($2118: VRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRC} // Set Source Offset
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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lda.b #{SRC} >> 16 // Set Source Bank
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sta.w REG_A1B{CHAN} // $43X4: Source Bank
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ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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}
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//========================================================
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// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride
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//========================================================
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// SRC: 24-Bit Address Of Source Data
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// DEST: 16-Bit VRAM Destination (WORD Address)
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// SIZE: Size Of Data (BYTE Size)
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// STRIDE: Dest Offset Stride
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// COUNT: Number Of DMA Transfers
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) {
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lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
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sta.w REG_VMAIN // $2115: Video Port Control
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lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
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sta.w REG_DMAP{CHAN} // $43X0: DMA Control
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lda.b #$18 // Set Destination Register ($2118: VRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRC} // Set Source Offset
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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lda.b #{SRC} >> 16 // Set Source Bank
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sta.w REG_A1B{CHAN} // $43X4: Source Bank
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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-
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stx.w REG_VMADDL // $2116: VRAM
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rep #$20 // Set 16-Bit Accumulator
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txa // A = X
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clc // Clear Carry Flag
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adc.w #{STRIDE} >> 1
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tax // X = A
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lda.w #{SIZE} // Set Size In Bytes To DMA Transfer
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sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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sep #$20 // Set 8-Bit Accumulator
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1
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bne -
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}
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//======================================
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// UpdateVRAM - Update GFX Data To VRAM
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//======================================
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// SRC: 24-Bit Address Of Source Data
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// DEST: 16-Bit VRAM Destination (WORD Address)
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// SIZE: Size Of Data (BYTE Size)
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro UpdateVRAM(SRC, DEST, SIZE, CHAN) {
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lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
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sta.w REG_VMAIN // $2115: Video Port Control
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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stx.w REG_VMADDL // $2116: VRAM
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lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
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sta.w REG_DMAP{CHAN} // $43X0: DMA Control
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lda.b #$18 // Set Destination Register ($2118: VRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRC} // Set Source Offset
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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lda.b #{SRC} >> 16 // Set Source Bank
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sta.w REG_A1B{CHAN} // $43X4: Source Bank
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ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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-
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bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
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bpl - // Wait For V-Blank Period Flag
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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}
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//===========================================
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// LoadM7VRAM - Load Mode 7 GFX Data To VRAM
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//===========================================
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// SRCMAP: 24-Bit Address Of Source Map Data
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// SRCTILES: 24-Bit Address Of Source Tile Data
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// DEST: 16-Bit VRAM Destination (WORD Address)
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// SIZEMAP: Size Of Map Data (BYTE Size)
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// SIZETILES: Size Of Tile Data (BYTE Size)
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) {
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// Load Mode7 Map Data To VRAM
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stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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stx.w REG_VMADDL // $2116: VRAM
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stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
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lda.b #$18 // Set Destination Register ($2118: VRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRCMAP} // Set Source Offset (Map)
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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lda.b #{SRCMAP} >> 16 // Set Source Bank
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sta.w REG_A1B{CHAN} // $43X4: Source Bank
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ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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// Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map)
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lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
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sta.w REG_VMAIN // $2115: Video Port Control
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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stx.w REG_VMADDL // $2116: VRAM
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lda.b #$19 // Set Destination Register ($2119: VRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRCTILES} // Set Source Offset (Tiles)
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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}
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//=============================================
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// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes
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//=============================================
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// SRCTILES: 24-Bit Address Of Source Tile Data
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// DEST: 16-Bit VRAM Destination (WORD Address)
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// SIZETILES: Size Of Tile Data (BYTE Size)
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
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stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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stx.w REG_VMADDL // $2116: VRAM
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stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
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lda.b #$18 // Set Destination Register ($2118: VRAM Write)
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sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
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ldx.w #{SRCTILES} // Set Source Offset
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stx.w REG_A1T{CHAN}L // $43X2: DMA Source
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lda.b #{SRCTILES} >> 16 // Set Source Bank
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sta.w REG_A1B{CHAN} // $43X4: Source Bank
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ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
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stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
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lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
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sta.w REG_MDMAEN // $420B: DMA Enable
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}
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//=============================================
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// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes
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//=============================================
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// SRCTILES: 24-Bit Address Of Source Tile Data
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// DEST: 16-Bit VRAM Destination (WORD Address)
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// SIZETILES: Size Of Tile Data (BYTE Size)
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// CHAN: DMA Channel To Transfer Data (0..7)
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macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
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lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
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sta.w REG_VMAIN // $2115: Video Port Control
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ldx.w #{DEST} >> 1 // Set VRAM Destination
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stx.w REG_VMADDL // $2116: VRAM
|
|
|
|
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
|
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
|
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
|
ldx.w #{SRCTILES} // Set Source Offset
|
|
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
|
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
|
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
|
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
|
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
|
|
|
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
|
sta.w REG_MDMAEN // $420B: DMA Enable
|
|
}
|
|
|
|
//===============================================
|
|
// BGScroll8 - Scroll GFX BG From Memory (8-Bit)
|
|
//===============================================
|
|
// BGSCR: Source BG Scroll Position
|
|
// BGPOS: Destination BG Pos Register
|
|
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
|
macro BGScroll8(BGSCR, BGPOS, DIR) {
|
|
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte
|
|
lda {BGSCR} // Load BG Scroll Position Low Byte
|
|
sta {BGPOS} // Store BG Scroll Position Low Byte
|
|
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
|
}
|
|
|
|
//=================================================
|
|
// BGScroll16 - Scroll GFX BG From Memory (16-Bit)
|
|
//=================================================
|
|
// BGSCR: Source BG Scroll Position
|
|
// BGPOS: Destination BG Pos Register
|
|
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
|
macro BGScroll16(BGSCR, BGPOS, DIR) {
|
|
rep #$38 // Set 16-Bit Accumulator & Index
|
|
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word
|
|
sep #$20 // Set 8-Bit Accumulator
|
|
lda {BGSCR} // Load BG Scroll Position Low Byte
|
|
sta {BGPOS} // Store BG Scroll Position Low Byte
|
|
lda {BGSCR} + 1 // Load BG Scroll Position High Byte
|
|
sta {BGPOS} // Store BG Scroll Position High Byte
|
|
}
|
|
|
|
//===============================================
|
|
// BGScroll8I - Scroll GFX BG From Index (8-Bit)
|
|
//===============================================
|
|
// REG: Source Index Register (x, y)
|
|
// BGPOS: Destination BG Position Register
|
|
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
|
macro BGScroll8I(REG, BGPOS, DIR) {
|
|
{DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte
|
|
t{REG}a // Swaps 8-Bit Index To 8-Bit A
|
|
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
|
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
|
}
|
|
|
|
//=================================================
|
|
// BGScroll16I - Scroll GFX BG From Index (16-Bit)
|
|
//=================================================
|
|
// REG: Source Index Register (x, y)
|
|
// BGPOS: Destination BG Position Register
|
|
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
|
macro BGScroll16I(REG, BGPOS, DIR) {
|
|
{DIR}{REG} // Decrement Or Increment BG Scroll Position Word
|
|
rep #$38 // Set 16-Bit Accumulator & Index
|
|
t{REG}a // Swaps 16-Bit Index To 16-Bit A
|
|
sep #$20 // Set 8-Bit Accumulator
|
|
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
|
xba // Exchange B & A Accumulators
|
|
sta {BGPOS} // Store A To BG Scroll Position High Byte
|
|
}
|
|
|
|
//======================================
|
|
// Mode7CALC - Mode7 Matrix Calculation
|
|
//======================================
|
|
// A: Mode7 COS A Word
|
|
// B: Mode7 SIN A Word
|
|
// C: Mode7 SIN B Word
|
|
// D: Mode7 COS B Word
|
|
// ANGLE: Mode7 Angle Byte
|
|
// SX: Mode7 Scale X Word
|
|
// SY: Mode7 Scale Y Word
|
|
// SINCOS: Mode7 SINCOS Table
|
|
macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) {
|
|
lda.b {ANGLE} // Load Angle To A
|
|
tax // Transfer A To X
|
|
|
|
// Calculate B & C (SIN)
|
|
// B
|
|
lda.b {SX} // Scale X
|
|
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
|
lda.b {SX} + 1
|
|
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
|
lda.w {SINCOS},x // SIN(X)
|
|
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
|
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
|
sty.w {B}
|
|
// C
|
|
lda.b {SY} // Scale Y
|
|
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
|
lda.b {SY} + 1 // High Byte
|
|
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
|
lda.w {SINCOS},x // SIN(X)
|
|
eor.b #$FF // Make Negative
|
|
inc
|
|
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
|
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
|
sty.w {C}
|
|
|
|
// Change X Index To Point To COS Values (X + 64)
|
|
txa // Transfer X Index To A
|
|
clc // Clear Carry Flag
|
|
adc.b #64 // Add 64 With Carry
|
|
tax // Transfer A To X Index
|
|
|
|
// Calculate A & D (COS)
|
|
// A
|
|
lda.b {SX} // Scale X
|
|
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
|
lda.b {SX} + 1
|
|
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
|
lda.w {SINCOS},x // COS(X)
|
|
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
|
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
|
sty.w {A}
|
|
// D
|
|
lda.b {SY} // Scale Y
|
|
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
|
lda.b {SY} + 1
|
|
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
|
lda.w {SINCOS},x // COS(X)
|
|
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
|
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
|
sty.w {D}
|
|
|
|
// Store Result To Matrix
|
|
lda.b {A}
|
|
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
|
lda.b {A} + 1
|
|
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
|
|
|
lda.b {B}
|
|
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
|
lda.b {B} + 1
|
|
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
|
|
|
lda.b {C}
|
|
sta.w REG_M7C // $211D: MODE7 SINE B
|
|
lda.b {C} + 1
|
|
sta.w REG_M7C // $211D: MODE7 SINE B
|
|
|
|
lda.b {D}
|
|
sta.w REG_M7D // $211E: MODE7 COSINE B
|
|
lda.b {D} + 1
|
|
sta.w REG_M7D // $211E: MODE7 COSINE B
|
|
} |