mirror of
https://github.com/TomHarte/CLK.git
synced 2025-04-06 10:38:16 +00:00
Takes a swing at incorporating krom's 65816 test suite. At least as far as ADC.
This commit is contained in:
Thomas Harte
parent
0178aaee2b
commit
3889646d6b
@ -458,6 +458,54 @@
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@ -1324,6 +1372,54 @@
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@ -2022,9 +2118,11 @@
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@ -3031,6 +3129,251 @@
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|
||||
4B8DF5242550D91400F3433C /* CPUROL-trace_compare.log */,
|
||||
4B8DF5252550D91400F3433C /* CPUBIT-trace_compare.log */,
|
||||
4B8DF5262550D91400F3433C /* CPUROR-trace_compare.log */,
|
||||
4B8DF5272550D91400F3433C /* CPUEOR-trace_compare.log */,
|
||||
4B8DF5282550D91400F3433C /* CPUORA-trace_compare.log */,
|
||||
4B8DF5292550D91400F3433C /* CPUDEC-trace_compare.log */,
|
||||
4B8DF52A2550D91400F3433C /* CPUAND-trace_compare.log */,
|
||||
4B8DF52B2550D91400F3433C /* CPUINC-trace_compare.log */,
|
||||
4B8DF52C2550D91400F3433C /* CPUMOV-trace_compare.log */,
|
||||
4B8DF52D2550D91400F3433C /* CPUBRA-trace_compare.log */,
|
||||
4B8DF52E2550D91400F3433C /* CPUASL-trace_compare.log */,
|
||||
4B8DF52F2550D91400F3433C /* CPUPSR-trace_compare.log */,
|
||||
4B8DF5302550D91400F3433C /* CPUCMP-trace_compare.log */,
|
||||
4B8DF5312550D91400F3433C /* CPUMSC-trace_compare.log */,
|
||||
4B8DF5322550D91400F3433C /* CPUSBC-trace_compare.log */,
|
||||
4B8DF5332550D91400F3433C /* CPUPHL-trace_compare.log */,
|
||||
4B8DF5342550D91400F3433C /* CPUJMP-trace_compare.log */,
|
||||
4B8DF5352550D91400F3433C /* CPURET-trace_compare.log */,
|
||||
4B8DF5362550D91400F3433C /* CPUTRN-trace_compare.log */,
|
||||
4B8DF5372550D91400F3433C /* CPUSTR-trace_compare.log */,
|
||||
4B8DF5382550D91400F3433C /* CPUADC-trace_compare.log */,
|
||||
);
|
||||
path = "emudev.de krom traces";
|
||||
sourceTree = "<group>";
|
||||
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|
||||
4B8DF5392550D91400F3433C /* krom 65816 */ = {
|
||||
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|
||||
children = (
|
||||
4B8DF53A2550D91400F3433C /* BRA */,
|
||||
4B8DF5442550D91500F3433C /* ROR */,
|
||||
4B8DF54E2550D91500F3433C /* CMP */,
|
||||
4B8DF5582550D91500F3433C /* RET */,
|
||||
4B8DF5622550D91500F3433C /* INC */,
|
||||
4B8DF56C2550D91500F3433C /* TRN */,
|
||||
4B8DF5762550D91500F3433C /* SBC */,
|
||||
4B8DF5802550D91500F3433C /* BIT */,
|
||||
4B8DF58A2550D91500F3433C /* ASL */,
|
||||
4B8DF5942550D91500F3433C /* LDR */,
|
||||
4B8DF59E2550D91500F3433C /* ORA */,
|
||||
4B8DF5A82550D91500F3433C /* JMP */,
|
||||
4B8DF5B22550D91500F3433C /* PHL */,
|
||||
4B8DF5BC2550D91500F3433C /* readme.md */,
|
||||
4B8DF5BD2550D91500F3433C /* AND */,
|
||||
4B8DF5C72550D91500F3433C /* ROL */,
|
||||
4B8DF5D12550D91500F3433C /* ADC */,
|
||||
4B8DF5DB2550D91500F3433C /* MSC */,
|
||||
4B8DF5E52550D91500F3433C /* DEC */,
|
||||
4B8DF5EF2550D91500F3433C /* PSR */,
|
||||
4B8DF5F92550D91600F3433C /* STR */,
|
||||
4B8DF6032550D91600F3433C /* LSR */,
|
||||
4B8DF60D2550D91600F3433C /* EOR */,
|
||||
4B8DF6172550D91600F3433C /* MOV */,
|
||||
);
|
||||
path = "krom 65816";
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF53A2550D91400F3433C /* BRA */ = {
|
||||
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|
||||
children = (
|
||||
4B8DF53D2550D91500F3433C /* CPUBRA.sfc */,
|
||||
);
|
||||
path = BRA;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5442550D91500F3433C /* ROR */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5462550D91500F3433C /* CPUROR.sfc */,
|
||||
);
|
||||
path = ROR;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF54E2550D91500F3433C /* CMP */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5502550D91500F3433C /* CPUCMP.sfc */,
|
||||
);
|
||||
path = CMP;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5582550D91500F3433C /* RET */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF55A2550D91500F3433C /* CPURET.sfc */,
|
||||
);
|
||||
path = RET;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5622550D91500F3433C /* INC */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5642550D91500F3433C /* CPUINC.sfc */,
|
||||
);
|
||||
path = INC;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF56C2550D91500F3433C /* TRN */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF56E2550D91500F3433C /* CPUTRN.sfc */,
|
||||
);
|
||||
path = TRN;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5762550D91500F3433C /* SBC */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5772550D91500F3433C /* CPUSBC.sfc */,
|
||||
);
|
||||
path = SBC;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5802550D91500F3433C /* BIT */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5832550D91500F3433C /* CPUBIT.sfc */,
|
||||
);
|
||||
path = BIT;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF58A2550D91500F3433C /* ASL */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5932550D91500F3433C /* CPUASL.sfc */,
|
||||
);
|
||||
path = ASL;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5942550D91500F3433C /* LDR */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5962550D91500F3433C /* CPULDR.sfc */,
|
||||
);
|
||||
path = LDR;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF59E2550D91500F3433C /* ORA */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5A62550D91500F3433C /* CPUORA.sfc */,
|
||||
);
|
||||
path = ORA;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5A82550D91500F3433C /* JMP */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5B02550D91500F3433C /* CPUJMP.sfc */,
|
||||
);
|
||||
path = JMP;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5B22550D91500F3433C /* PHL */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5BB2550D91500F3433C /* CPUPHL.sfc */,
|
||||
);
|
||||
path = PHL;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5BD2550D91500F3433C /* AND */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5C42550D91500F3433C /* CPUAND.sfc */,
|
||||
);
|
||||
path = AND;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5C72550D91500F3433C /* ROL */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5C82550D91500F3433C /* CPUROL.sfc */,
|
||||
);
|
||||
path = ROL;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5D12550D91500F3433C /* ADC */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5D92550D91500F3433C /* CPUADC.sfc */,
|
||||
);
|
||||
path = ADC;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5DB2550D91500F3433C /* MSC */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5E42550D91500F3433C /* CPUMSC.sfc */,
|
||||
);
|
||||
path = MSC;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5E52550D91500F3433C /* DEC */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5E62550D91500F3433C /* CPUDEC.sfc */,
|
||||
);
|
||||
path = DEC;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5EF2550D91500F3433C /* PSR */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF5F82550D91600F3433C /* CPUPSR.sfc */,
|
||||
);
|
||||
path = PSR;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF5F92550D91600F3433C /* STR */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF6012550D91600F3433C /* CPUSTR.sfc */,
|
||||
);
|
||||
path = STR;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF6032550D91600F3433C /* LSR */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF6052550D91600F3433C /* CPULSR.sfc */,
|
||||
);
|
||||
path = LSR;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF60D2550D91600F3433C /* EOR */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF6102550D91600F3433C /* CPUEOR.sfc */,
|
||||
);
|
||||
path = EOR;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8DF6172550D91600F3433C /* MOV */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4B8DF6192550D91600F3433C /* CPUMOV.sfc */,
|
||||
);
|
||||
path = MOV;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4B8EF6051FE5AF830076CCDD /* Implementation */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
@ -3473,6 +3816,7 @@
|
||||
children = (
|
||||
4B85322922778E4200F26553 /* Comparative68000.hpp */,
|
||||
4B90467222C6FA31000E2074 /* TestRunner68000.hpp */,
|
||||
4B90467522C6FD6E000E2074 /* 68000ArithmeticTests.mm */,
|
||||
4B9D0C4A22C7D70900DE1AD3 /* 68000BCDTests.mm */,
|
||||
4B90467322C6FADD000E2074 /* 68000BitwiseTests.mm */,
|
||||
4B680CE123A5553100451D43 /* 68000ComparativeTests.mm */,
|
||||
@ -3501,6 +3845,7 @@
|
||||
4BC751B11D157E61006C31D9 /* 6522Tests.swift */,
|
||||
4B1E85801D176468001EF87D /* 6532Tests.swift */,
|
||||
4B4F478925367EDC004245B8 /* 65816AddressingTests.swift */,
|
||||
4B8DF5132550D62900F3433C /* 65816kromTests.swift */,
|
||||
4BB73EB61B587A5100552FC2 /* AllSuiteATests.swift */,
|
||||
4B049CDC1DA3C82F00322067 /* BCDTest.swift */,
|
||||
4B3BA0C21D318AEB005DD7A7 /* C1540Tests.swift */,
|
||||
@ -3516,7 +3861,6 @@
|
||||
4BFCA12A1ECBE7C400AC40C1 /* ZexallTests.swift */,
|
||||
4B3BA0C41D318B44005DD7A7 /* Bridges */,
|
||||
4B1414631B588A1100E04248 /* Test Binaries */,
|
||||
4B90467522C6FD6E000E2074 /* 68000ArithmeticTests.mm */,
|
||||
);
|
||||
path = "Clock SignalTests";
|
||||
sourceTree = "<group>";
|
||||
@ -4236,13 +4580,16 @@
|
||||
4BB299521B587D8400A49093 /* eoray in Resources */,
|
||||
4BB299411B587D8400A49093 /* cpyb in Resources */,
|
||||
4BB299A61B587D8400A49093 /* phan in Resources */,
|
||||
4B8DF6352550D91600F3433C /* CPUTRN-trace_compare.log in Resources */,
|
||||
4BB299D91B587D8400A49093 /* staix in Resources */,
|
||||
4BB299EA1B587D8400A49093 /* trap14 in Resources */,
|
||||
4BB2990F1B587D8400A49093 /* asoiy in Resources */,
|
||||
4B8DF6592550D91600F3433C /* CPUINC.sfc in Resources */,
|
||||
4BB298FF1B587D8400A49093 /* andb in Resources */,
|
||||
4BB299021B587D8400A49093 /* andz in Resources */,
|
||||
4BB299E31B587D8400A49093 /* taxn in Resources */,
|
||||
4BB299551B587D8400A49093 /* eoriy in Resources */,
|
||||
4B8DF62B2550D91600F3433C /* CPUMOV-trace_compare.log in Resources */,
|
||||
4BB298F91B587D8400A49093 /* adczx in Resources */,
|
||||
4BB299F21B587D8400A49093 /* trap6 in Resources */,
|
||||
4B670A9B2401CB8400D4E002 /* z80memptr.tap in Resources */,
|
||||
@ -4252,6 +4599,7 @@
|
||||
4BB299AF1B587D8400A49093 /* rlaz in Resources */,
|
||||
4BB2999C1B587D8400A49093 /* nopzx in Resources */,
|
||||
4BB299A01B587D8400A49093 /* oraay in Resources */,
|
||||
4B8DF6E32550D91700F3433C /* CPUEOR.sfc in Resources */,
|
||||
4BB299C01B587D8400A49093 /* rraz in Resources */,
|
||||
4BB299771B587D8400A49093 /* ldab in Resources */,
|
||||
4BB299031B587D8400A49093 /* andzx in Resources */,
|
||||
@ -4265,6 +4613,7 @@
|
||||
4BB299881B587D8400A49093 /* lseax in Resources */,
|
||||
4BB299B91B587D8400A49093 /* rorz in Resources */,
|
||||
4BB299F61B587D8400A49093 /* tsxn in Resources */,
|
||||
4B8DF6682550D91600F3433C /* CPUSBC.sfc in Resources */,
|
||||
4BB298F11B587D8400A49093 /* start in Resources */,
|
||||
4BDA00DD22E622C200AC3CD0 /* ROMImages in Resources */,
|
||||
4BB299061B587D8400A49093 /* asla in Resources */,
|
||||
@ -4276,6 +4625,7 @@
|
||||
4BB299431B587D8400A49093 /* dcma in Resources */,
|
||||
4BB298FD1B587D8400A49093 /* andax in Resources */,
|
||||
4B85322D227793CB00F26553 /* etos192uk.trace.txt.gz in Resources */,
|
||||
4B8DF6262550D91600F3433C /* CPUEOR-trace_compare.log in Resources */,
|
||||
4BB299401B587D8400A49093 /* cpya in Resources */,
|
||||
4BB299BE1B587D8400A49093 /* rraix in Resources */,
|
||||
4BB299E41B587D8400A49093 /* tayn in Resources */,
|
||||
@ -4286,12 +4636,14 @@
|
||||
4BB299361B587D8400A49093 /* cmpiy in Resources */,
|
||||
4BB299B01B587D8400A49093 /* rlazx in Resources */,
|
||||
4BB2999F1B587D8400A49093 /* oraax in Resources */,
|
||||
4B8DF6A92550D91700F3433C /* CPUROL.sfc in Resources */,
|
||||
4BB299B71B587D8400A49093 /* rorax in Resources */,
|
||||
4B670AB02401CB8400D4E002 /* z80full.tap in Resources */,
|
||||
4BB299DB1B587D8400A49093 /* staz in Resources */,
|
||||
4BB299961B587D8400A49093 /* nmi in Resources */,
|
||||
4BB299241B587D8400A49093 /* cia1ta in Resources */,
|
||||
4BB2990E1B587D8400A49093 /* asoix in Resources */,
|
||||
4B8DF6D72550D91700F3433C /* CPUSTR.sfc in Resources */,
|
||||
4BE211DE253E4E4800435408 /* 65C02_no_Rockwell_test.bin in Resources */,
|
||||
4BB299F51B587D8400A49093 /* trap9 in Resources */,
|
||||
4BB299C81B587D8400A49093 /* sbcb(eb) in Resources */,
|
||||
@ -4299,6 +4651,7 @@
|
||||
4BB299D01B587D8400A49093 /* sein in Resources */,
|
||||
4BB299151B587D8400A49093 /* axszy in Resources */,
|
||||
4BB2994D1B587D8400A49093 /* deczx in Resources */,
|
||||
4B8DF63A2550D91600F3433C /* CPUBRA.sfc in Resources */,
|
||||
4BB299B11B587D8400A49093 /* rola in Resources */,
|
||||
4BB299CE1B587D8400A49093 /* secn in Resources */,
|
||||
4BB298F31B587D8400A49093 /* adcax in Resources */,
|
||||
@ -4307,6 +4660,7 @@
|
||||
4BB299E61B587D8400A49093 /* trap10 in Resources */,
|
||||
4BB299651B587D8400A49093 /* insz in Resources */,
|
||||
4B44EBF91DC9898E00A7820C /* BCDTEST_beeb in Resources */,
|
||||
4B8DF6272550D91600F3433C /* CPUORA-trace_compare.log in Resources */,
|
||||
4BB299161B587D8400A49093 /* bccr in Resources */,
|
||||
4BB299211B587D8400A49093 /* bvsr in Resources */,
|
||||
4BB2991F1B587D8400A49093 /* brkn in Resources */,
|
||||
@ -4316,6 +4670,7 @@
|
||||
4BB299511B587D8400A49093 /* eorax in Resources */,
|
||||
4BB299A11B587D8400A49093 /* orab in Resources */,
|
||||
4BB298F81B587D8400A49093 /* adcz in Resources */,
|
||||
4B8DF6D02550D91700F3433C /* CPUPSR.sfc in Resources */,
|
||||
4BB299EC1B587D8400A49093 /* trap16 in Resources */,
|
||||
4BB299741B587D8400A49093 /* ldaa in Resources */,
|
||||
4BB299871B587D8400A49093 /* lsea in Resources */,
|
||||
@ -4325,6 +4680,7 @@
|
||||
4BB17D4E1ED7909F00ABD1E1 /* tests.expected.json in Resources */,
|
||||
4BB2998F1B587D8400A49093 /* lsrax in Resources */,
|
||||
4BB299001B587D8400A49093 /* andix in Resources */,
|
||||
4B8DF6242550D91600F3433C /* CPUBIT-trace_compare.log in Resources */,
|
||||
4BB2993A1B587D8400A49093 /* cnto2 in Resources */,
|
||||
4BB298FA1B587D8400A49093 /* alrb in Resources */,
|
||||
4BB299C71B587D8400A49093 /* sbcb in Resources */,
|
||||
@ -4333,7 +4689,10 @@
|
||||
4BB299AB1B587D8400A49093 /* rlaax in Resources */,
|
||||
4BB299B81B587D8400A49093 /* rorn in Resources */,
|
||||
4BB2997A1B587D8400A49093 /* ldaz in Resources */,
|
||||
4B8DF6212550D91600F3433C /* CPULDR-trace_compare.log in Resources */,
|
||||
4BB299381B587D8400A49093 /* cmpzx in Resources */,
|
||||
4B8DF6A02550D91700F3433C /* readme.md in Resources */,
|
||||
4B8DF6A62550D91700F3433C /* CPUAND.sfc in Resources */,
|
||||
4BB2997F1B587D8400A49093 /* ldxz in Resources */,
|
||||
4BB2992D1B587D8400A49093 /* clcn in Resources */,
|
||||
4BB299E01B587D8400A49093 /* stya in Resources */,
|
||||
@ -4346,10 +4705,12 @@
|
||||
4B670AB12401CB8400D4E002 /* z80docflags.tap in Resources */,
|
||||
4BB299D51B587D8400A49093 /* shyax in Resources */,
|
||||
4BB2992F1B587D8400A49093 /* clin in Resources */,
|
||||
4B8DF6332550D91600F3433C /* CPUJMP-trace_compare.log in Resources */,
|
||||
4BB299D21B587D8400A49093 /* shaiy in Resources */,
|
||||
4BB2991A1B587D8400A49093 /* bitz in Resources */,
|
||||
4BB299531B587D8400A49093 /* eorb in Resources */,
|
||||
4BB299661B587D8400A49093 /* inszx in Resources */,
|
||||
4B8DF62D2550D91600F3433C /* CPUASL-trace_compare.log in Resources */,
|
||||
4BB299101B587D8400A49093 /* asoz in Resources */,
|
||||
4BB2998B1B587D8400A49093 /* lseiy in Resources */,
|
||||
4B9252CE1E74D28200B76AF1 /* Atari ROMs in Resources */,
|
||||
@ -4364,6 +4725,7 @@
|
||||
4BB299F81B587D8400A49093 /* txsn in Resources */,
|
||||
4BB299E81B587D8400A49093 /* trap12 in Resources */,
|
||||
4BB299891B587D8400A49093 /* lseay in Resources */,
|
||||
4B8DF62C2550D91600F3433C /* CPUBRA-trace_compare.log in Resources */,
|
||||
4BB2997B1B587D8400A49093 /* ldazx in Resources */,
|
||||
4BB2990D1B587D8400A49093 /* asoay in Resources */,
|
||||
4BB299AD1B587D8400A49093 /* rlaix in Resources */,
|
||||
@ -4380,21 +4742,25 @@
|
||||
4BB299C61B587D8400A49093 /* sbcay in Resources */,
|
||||
4BB299601B587D8400A49093 /* insa in Resources */,
|
||||
4BB299951B587D8400A49093 /* mmufetch in Resources */,
|
||||
4B8DF62E2550D91600F3433C /* CPUPSR-trace_compare.log in Resources */,
|
||||
4BB17D4F1ED7909F00ABD1E1 /* tests.in.json in Resources */,
|
||||
4BB299A71B587D8400A49093 /* phpn in Resources */,
|
||||
4BB299CC1B587D8400A49093 /* sbczx in Resources */,
|
||||
4BB299C91B587D8400A49093 /* sbcix in Resources */,
|
||||
4BB2991B1B587D8400A49093 /* bmir in Resources */,
|
||||
4B8DF6DA2550D91700F3433C /* CPULSR.sfc in Resources */,
|
||||
4BB299EF1B587D8400A49093 /* trap3 in Resources */,
|
||||
4BB299D31B587D8400A49093 /* shsay in Resources */,
|
||||
4BB299AE1B587D8400A49093 /* rlaiy in Resources */,
|
||||
4BB299181B587D8400A49093 /* beqr in Resources */,
|
||||
4BB299311B587D8400A49093 /* cmpa in Resources */,
|
||||
4B8DF6282550D91600F3433C /* CPUDEC-trace_compare.log in Resources */,
|
||||
4BB2997E1B587D8400A49093 /* ldxb in Resources */,
|
||||
4BB298F51B587D8400A49093 /* adcb in Resources */,
|
||||
4BB299981B587D8400A49093 /* nopax in Resources */,
|
||||
4BB299931B587D8400A49093 /* lxab in Resources */,
|
||||
4BB299F01B587D8400A49093 /* trap4 in Resources */,
|
||||
4B8DF6722550D91600F3433C /* CPUBIT.sfc in Resources */,
|
||||
4BB299451B587D8400A49093 /* dcmay in Resources */,
|
||||
4BB299081B587D8400A49093 /* asln in Resources */,
|
||||
4BB2996E1B587D8400A49093 /* laxa in Resources */,
|
||||
@ -4406,7 +4772,9 @@
|
||||
4B670AA12401CB8400D4E002 /* z80doc.tap in Resources */,
|
||||
4BB299941B587D8400A49093 /* mmu in Resources */,
|
||||
4BB299E11B587D8400A49093 /* styz in Resources */,
|
||||
4B8DF6812550D91700F3433C /* CPULDR.sfc in Resources */,
|
||||
4BB299BA1B587D8400A49093 /* rorzx in Resources */,
|
||||
4B8DF6512550D91600F3433C /* CPURET.sfc in Resources */,
|
||||
4BB299491B587D8400A49093 /* dcmzx in Resources */,
|
||||
4BB299AC1B587D8400A49093 /* rlaay in Resources */,
|
||||
4BB299131B587D8400A49093 /* axsix in Resources */,
|
||||
@ -4416,8 +4784,10 @@
|
||||
4BE9A6B11EDE293000CBCB47 /* zexdoc.com in Resources */,
|
||||
4BB2994A1B587D8400A49093 /* deca in Resources */,
|
||||
4BB299CA1B587D8400A49093 /* sbciy in Resources */,
|
||||
4B8DF6252550D91600F3433C /* CPUROR-trace_compare.log in Resources */,
|
||||
4BB2993D1B587D8400A49093 /* cpxa in Resources */,
|
||||
4BB299721B587D8400A49093 /* laxz in Resources */,
|
||||
4B8DF6312550D91600F3433C /* CPUSBC-trace_compare.log in Resources */,
|
||||
4BB299011B587D8400A49093 /* andiy in Resources */,
|
||||
4BB2992B1B587D8400A49093 /* cia2tb in Resources */,
|
||||
4BB299221B587D8400A49093 /* cia1pb6 in Resources */,
|
||||
@ -4425,6 +4795,7 @@
|
||||
4BB2996C1B587D8400A49093 /* jsrw in Resources */,
|
||||
4BB299EE1B587D8400A49093 /* trap2 in Resources */,
|
||||
4BB299921B587D8400A49093 /* lsrzx in Resources */,
|
||||
4B8DF6232550D91600F3433C /* CPUROL-trace_compare.log in Resources */,
|
||||
4BB299371B587D8400A49093 /* cmpz in Resources */,
|
||||
4BB298FC1B587D8400A49093 /* anda in Resources */,
|
||||
4BB299CB1B587D8400A49093 /* sbcz in Resources */,
|
||||
@ -4445,28 +4816,41 @@
|
||||
4BB2995E1B587D8400A49093 /* incz in Resources */,
|
||||
4BB299791B587D8400A49093 /* ldaiy in Resources */,
|
||||
4BB299A31B587D8400A49093 /* oraiy in Resources */,
|
||||
4B8DF68E2550D91700F3433C /* CPUORA.sfc in Resources */,
|
||||
4BB2990B1B587D8400A49093 /* asoa in Resources */,
|
||||
4BB299DA1B587D8400A49093 /* staiy in Resources */,
|
||||
4BB299761B587D8400A49093 /* ldaay in Resources */,
|
||||
4B8DF6EA2550D91700F3433C /* CPUMOV.sfc in Resources */,
|
||||
4BB299631B587D8400A49093 /* insix in Resources */,
|
||||
4BB299B61B587D8400A49093 /* rora in Resources */,
|
||||
4BB299BC1B587D8400A49093 /* rraax in Resources */,
|
||||
4BB299B21B587D8400A49093 /* rolax in Resources */,
|
||||
4B8DF6342550D91600F3433C /* CPURET-trace_compare.log in Resources */,
|
||||
4BB299481B587D8400A49093 /* dcmz in Resources */,
|
||||
4B8DF6492550D91600F3433C /* CPUCMP.sfc in Resources */,
|
||||
4BB2996A1B587D8400A49093 /* jmpi in Resources */,
|
||||
4B8DF6322550D91600F3433C /* CPUPHL-trace_compare.log in Resources */,
|
||||
4BB299831B587D8400A49093 /* ldyb in Resources */,
|
||||
4BB299911B587D8400A49093 /* lsrz in Resources */,
|
||||
4BB299A51B587D8400A49093 /* orazx in Resources */,
|
||||
4BB299B31B587D8400A49093 /* roln in Resources */,
|
||||
4B8DF6C12550D91700F3433C /* CPUDEC.sfc in Resources */,
|
||||
4B8DF6302550D91600F3433C /* CPUMSC-trace_compare.log in Resources */,
|
||||
4BB2995D1B587D8400A49093 /* incax in Resources */,
|
||||
4BB2992E1B587D8400A49093 /* cldn in Resources */,
|
||||
4B8DF62F2550D91600F3433C /* CPUCMP-trace_compare.log in Resources */,
|
||||
4B8DF6412550D91600F3433C /* CPUROR.sfc in Resources */,
|
||||
4BB299691B587D8400A49093 /* irq in Resources */,
|
||||
4B8DF6962550D91700F3433C /* CPUJMP.sfc in Resources */,
|
||||
4BB299851B587D8400A49093 /* ldyzx in Resources */,
|
||||
4BB299F31B587D8400A49093 /* trap7 in Resources */,
|
||||
4B8DF6292550D91600F3433C /* CPUAND-trace_compare.log in Resources */,
|
||||
4BB299571B587D8400A49093 /* eorzx in Resources */,
|
||||
4BB299701B587D8400A49093 /* laxix in Resources */,
|
||||
4B8DF6372550D91600F3433C /* CPUADC-trace_compare.log in Resources */,
|
||||
4BB299441B587D8400A49093 /* dcmax in Resources */,
|
||||
4BB2996F1B587D8400A49093 /* laxay in Resources */,
|
||||
4B8DF6C02550D91700F3433C /* CPUMSC.sfc in Resources */,
|
||||
4BB298F71B587D8400A49093 /* adciy in Resources */,
|
||||
4BB299271B587D8400A49093 /* cia1tb123 in Resources */,
|
||||
4BB299C51B587D8400A49093 /* sbcax in Resources */,
|
||||
@ -4476,6 +4860,7 @@
|
||||
4BB298F61B587D8400A49093 /* adcix in Resources */,
|
||||
4BB299261B587D8400A49093 /* cia1tb in Resources */,
|
||||
4BB2997C1B587D8400A49093 /* ldxa in Resources */,
|
||||
4B8DF6362550D91600F3433C /* CPUSTR-trace_compare.log in Resources */,
|
||||
4BB299A41B587D8400A49093 /* oraz in Resources */,
|
||||
4BB299611B587D8400A49093 /* insax in Resources */,
|
||||
4BB299351B587D8400A49093 /* cmpix in Resources */,
|
||||
@ -4486,8 +4871,10 @@
|
||||
4BB299091B587D8400A49093 /* aslz in Resources */,
|
||||
4BB299ED1B587D8400A49093 /* trap17 in Resources */,
|
||||
4BB299731B587D8400A49093 /* laxzy in Resources */,
|
||||
4B8DF69F2550D91700F3433C /* CPUPHL.sfc in Resources */,
|
||||
4BB299F91B587D8400A49093 /* tyan in Resources */,
|
||||
4BB299DF1B587D8400A49093 /* stxzy in Resources */,
|
||||
4B8DF67F2550D91700F3433C /* CPUASL.sfc in Resources */,
|
||||
4BB299231B587D8400A49093 /* cia1pb7 in Resources */,
|
||||
4BB2998D1B587D8400A49093 /* lsezx in Resources */,
|
||||
4BB299811B587D8400A49093 /* ldya in Resources */,
|
||||
@ -4496,16 +4883,20 @@
|
||||
4BB299D11B587D8400A49093 /* shaay in Resources */,
|
||||
4BB299A21B587D8400A49093 /* oraix in Resources */,
|
||||
4BB299AA1B587D8400A49093 /* rlaa in Resources */,
|
||||
4B8DF6612550D91600F3433C /* CPUTRN.sfc in Resources */,
|
||||
4BB299541B587D8400A49093 /* eorix in Resources */,
|
||||
4BB2993C1B587D8400A49093 /* cputiming in Resources */,
|
||||
4BB2999E1B587D8400A49093 /* oraa in Resources */,
|
||||
4BB299D81B587D8400A49093 /* staay in Resources */,
|
||||
4B8DF62A2550D91600F3433C /* CPUINC-trace_compare.log in Resources */,
|
||||
4BB2993F1B587D8400A49093 /* cpxz in Resources */,
|
||||
4BB299861B587D8400A49093 /* loadth in Resources */,
|
||||
4BB299321B587D8400A49093 /* cmpax in Resources */,
|
||||
4BB2999A1B587D8400A49093 /* nopn in Resources */,
|
||||
4BB2996D1B587D8400A49093 /* lasay in Resources */,
|
||||
4BB299421B587D8400A49093 /* cpyz in Resources */,
|
||||
4B8DF6B72550D91700F3433C /* CPUADC.sfc in Resources */,
|
||||
4B8DF6222550D91600F3433C /* CPULSR-trace_compare.log in Resources */,
|
||||
4B680CE423A555CA00451D43 /* 68000 Comparative Tests in Resources */,
|
||||
4BB299DE1B587D8400A49093 /* stxz in Resources */,
|
||||
4BB2991C1B587D8400A49093 /* bner in Resources */,
|
||||
@ -5016,6 +5407,7 @@
|
||||
4B778F6223A5F35F0000D260 /* File.cpp in Sources */,
|
||||
4B778F3523A5F1040000D260 /* SCSI.cpp in Sources */,
|
||||
4BD388882239E198002D14B5 /* 68000Tests.mm in Sources */,
|
||||
4B8DF5142550D62A00F3433C /* 65816kromTests.swift in Sources */,
|
||||
4BA91E1D216D85BA00F79557 /* MasterSystemVDPTests.mm in Sources */,
|
||||
4B98A0611FFADCDE00ADF63B /* MSXStaticAnalyserTests.mm in Sources */,
|
||||
4BE34438238389E10058E78F /* AtariSTVideoTests.mm in Sources */,
|
||||
|
||||
106
OSBindings/Mac/Clock SignalTests/65816kromTests.swift
Normal file
106
OSBindings/Mac/Clock SignalTests/65816kromTests.swift
Normal file
@ -0,0 +1,106 @@
|
||||
//
|
||||
// krom65816Tests.swift
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 02/11/2020.
|
||||
// Copyright 2020 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
import Foundation
|
||||
import XCTest
|
||||
|
||||
// This utilises krom's SNES-centric 65816 tests, comparing step-by-step to
|
||||
// the traces offered by LilaQ at emudev.de as I don't want to implement a
|
||||
// SNES just for the sake of result inspection.
|
||||
//
|
||||
// So:
|
||||
// https://github.com/PeterLemon/SNES/tree/master/CPUTest/CPU for the tests;
|
||||
// https://emudev.de/q00-snes/65816-the-cpu/ for the traces.
|
||||
class Krom65816Tests: XCTestCase {
|
||||
|
||||
// MARK: - Test Machine
|
||||
|
||||
func runTest(_ name: String) {
|
||||
var testData: Data?
|
||||
if let filename = Bundle(for: type(of: self)).path(forResource: name, ofType: "sfc") {
|
||||
testData = try? Data(contentsOf: URL(fileURLWithPath: filename))
|
||||
}
|
||||
|
||||
var testOutput: String?
|
||||
if let filename = Bundle(for: type(of: self)).path(forResource: name + "-trace_compare", ofType: "log") {
|
||||
testOutput = try? String(contentsOf: URL(fileURLWithPath: filename))
|
||||
}
|
||||
|
||||
XCTAssertNotNil(testData)
|
||||
XCTAssertNotNil(testOutput)
|
||||
|
||||
let outputLines = testOutput!.components(separatedBy: "\r\n")
|
||||
|
||||
// Assumptions about the SFC file format follow; I couldn't find a spec but those
|
||||
// produced by krom appear just to be binary dumps. Fingers crossed!
|
||||
let machine = CSTestMachine6502(processor: .processor65816)
|
||||
machine.setData(testData!, atAddress: 0x8000)
|
||||
|
||||
// This reproduces the state seen at the first line of all of LilaQ's traces;
|
||||
// TODO: determine whether (i) this is the SNES state at reset, or merely how
|
||||
// some sort of BIOS leaves it; and (ii) if the former, whether I have post-reset
|
||||
// state incorrect. I strongly suspect it's a SNES-specific artefact?
|
||||
machine.setValue(0x8000, for: .programCounter)
|
||||
machine.setValue(0x0000, for: .A)
|
||||
machine.setValue(0x0000, for: .X)
|
||||
machine.setValue(0x0000, for: .Y)
|
||||
machine.setValue(0x00ff, for: .stackPointer)
|
||||
machine.setValue(0x34, for: .flags)
|
||||
|
||||
var lineNumber = 1
|
||||
for line in outputLines {
|
||||
machine.runForNumber(ofInstructions: 1)
|
||||
|
||||
// Formulate my 65816 state in the same form as the test machine
|
||||
var cpuState = ""
|
||||
let emulationFlag = machine.value(for: .emulationFlag) != 0
|
||||
cpuState += String(format: "%06x ", machine.value(for: .lastOperationAddress))
|
||||
cpuState += String(format: "A:%04x ", machine.value(for: .A))
|
||||
cpuState += String(format: "X:%04x ", machine.value(for: .X))
|
||||
cpuState += String(format: "Y:%04x ", machine.value(for: .Y))
|
||||
if emulationFlag {
|
||||
cpuState += String(format: "S:01%02x ", machine.value(for: .stackPointer))
|
||||
} else {
|
||||
cpuState += String(format: "S:%04x ", machine.value(for: .stackPointer))
|
||||
}
|
||||
cpuState += String(format: "D:%04x ", machine.value(for: .direct))
|
||||
cpuState += String(format: "DB:%02x ", machine.value(for: .dataBank))
|
||||
|
||||
let flags = machine.value(for: .flags)
|
||||
cpuState += (flags & 0x80) != 0 ? "N" : "n"
|
||||
cpuState += (flags & 0x40) != 0 ? "V" : "v"
|
||||
if emulationFlag {
|
||||
// These logs seem always to have the break flag set (?)
|
||||
cpuState += (flags & 0x20) != 0 ? "1" : "?"
|
||||
cpuState += "B" //(flags & 0x10) != 0 ? "B" : "b"
|
||||
} else {
|
||||
cpuState += (flags & 0x20) != 0 ? "M" : "m"
|
||||
cpuState += (flags & 0x10) != 0 ? "X" : "x"
|
||||
}
|
||||
cpuState += (flags & 0x08) != 0 ? "D" : "d"
|
||||
cpuState += (flags & 0x04) != 0 ? "I" : "i"
|
||||
cpuState += (flags & 0x02) != 0 ? "Z" : "z"
|
||||
cpuState += (flags & 0x01) != 0 ? "C" : "c"
|
||||
|
||||
cpuState += " "
|
||||
|
||||
XCTAssertEqual(cpuState, line, "Mismatch on line #\(lineNumber)")
|
||||
if cpuState != line {
|
||||
break
|
||||
}
|
||||
lineNumber += 1
|
||||
}
|
||||
}
|
||||
|
||||
// MARK: - Tests
|
||||
|
||||
func testADC() {
|
||||
runTest("CPUADC")
|
||||
}
|
||||
|
||||
}
|
||||
@ -39,6 +39,7 @@ extern const uint8_t CSTestMachine6502JamOpcode;
|
||||
|
||||
- (void)setData:(nonnull NSData *)data atAddress:(uint32_t)startAddress;
|
||||
- (void)runForNumberOfCycles:(int)cycles;
|
||||
- (void)runForNumberOfInstructions:(int)instructions;
|
||||
|
||||
- (void)setValue:(uint8_t)value forAddress:(uint32_t)address;
|
||||
- (uint8_t)valueForAddress:(uint32_t)address;
|
||||
|
||||
@ -114,4 +114,8 @@ static CPU::MOS6502::Register registerForRegister(CSTestMachine6502Register reg)
|
||||
_processor->run_for(Cycles(cycles));
|
||||
}
|
||||
|
||||
- (void)runForNumberOfInstructions:(int)instructions {
|
||||
_processor->run_for_instructions(instructions);
|
||||
}
|
||||
|
||||
@end
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,5 @@
|
||||
# LilaQ's traces of the krom 65816 Test Suite
|
||||
|
||||
These traces were obtained from https://emudev.de/q00-snes/65816-the-cpu/
|
||||
|
||||
Their licensing is unclear.
|
||||
5231
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/CPUADC.asm
Normal file
5231
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/CPUADC.asm
Normal file
File diff suppressed because it is too large
Load Diff
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/CPUADC.png
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/CPUADC.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.4 KiB |
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/CPUADC.sfc
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/CPUADC.sfc
Normal file
Binary file not shown.
957
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/Font8x8.asm
Normal file
957
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/Font8x8.asm
Normal file
@ -0,0 +1,957 @@
|
||||
fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes
|
||||
|
||||
// $20: Space " "
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $21: Exclamation mark "!"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $22: Quotation mark """
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $23: Cross hatch "#"
|
||||
db %00010100
|
||||
db %00010100
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $24: Dollar sign "$"
|
||||
db %00111100
|
||||
db %01101010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01010110
|
||||
db %00111100
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $25: Percent sign "%"
|
||||
db %00100010
|
||||
db %01010100
|
||||
db %00101000
|
||||
db %00010100
|
||||
db %00101010
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $26: Ampersand "&"
|
||||
db %00110000
|
||||
db %01001000
|
||||
db %00110010
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00110010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $27: Closing single quote "'"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $28: Opening parentheses "("
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
|
||||
// $29: Closing parentheses ")"
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
|
||||
// $2A: Asterisk "*"
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2B: Plus "+"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2C: Comma ","
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $2D: Hyphen "-"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2E: Period "."
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2F: Forward slash "/"
|
||||
db %00000010
|
||||
db %00000110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01100000
|
||||
db %01000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $30: 0
|
||||
db %00111010
|
||||
db %01100100
|
||||
db %01001010
|
||||
db %01010010
|
||||
db %00100110
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $31: 1
|
||||
db %00011000
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $32: 2
|
||||
db %00111000
|
||||
db %01001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $33: 3
|
||||
db %00111100
|
||||
db %01000110
|
||||
db %00011100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $34: 4
|
||||
db %00001100
|
||||
db %00011100
|
||||
db %00101100
|
||||
db %01001100
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $35: 5
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $36: 6
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $37: 7
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $38: 8
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $39: 9
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %00000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $3A: Colon ":"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3B: Semicolon ";"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $3C: Less than sign "<"
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3D: Equals sign "="
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3E: Greater than sign ">"
|
||||
db %00000000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3F: Question mark "?"
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
|
||||
// $40: At sign "@"
|
||||
db %01111100
|
||||
db %10000010
|
||||
db %10111010
|
||||
db %10101010
|
||||
db %10111110
|
||||
db %01000000
|
||||
db %00111110
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $41: A
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00100100
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $42: B
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $43: C
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $44: D
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $45: E
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $46: F
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $47: G
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $48: H
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $49: I
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4A: J
|
||||
db %00111110
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %01001100
|
||||
db %01111100
|
||||
db %00111000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4B: K
|
||||
db %01100110
|
||||
db %01101100
|
||||
db %01111000
|
||||
db %01111000
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4C: L
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4D: M
|
||||
db %01000010
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4E: N
|
||||
db %01000110
|
||||
db %01100110
|
||||
db %01110110
|
||||
db %01111110
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4F: O
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $50: P
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $51: Q
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100010
|
||||
db %01101010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $52: R
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $53: S
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $54: T
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $55: U
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $56: V
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00100100
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $57: W
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $58: X
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $59: Y
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5A: Z
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $5B: Opening square bracket "["
|
||||
db %00011100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011100
|
||||
|
||||
// $5C: Back slash "\"
|
||||
db %01000000
|
||||
db %01100000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00000110
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $5D: Closing square bracket "]"
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111000
|
||||
|
||||
// $5E: Caret "^"
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5F: Underscore "_"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %11111111
|
||||
|
||||
// $60: Opening single quote "`"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $61: a
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01100100
|
||||
db %01100100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $62: b
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00111100
|
||||
db %00110010
|
||||
db %00110010
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $63: c
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $64: d
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $65: e
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01101000
|
||||
db %01110010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $66: f
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011100
|
||||
db %00110010
|
||||
db %00110000
|
||||
db %01111100
|
||||
db %00110000
|
||||
db %00110000
|
||||
|
||||
// $67: g
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111010
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $68: h
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $69: i
|
||||
db %00110000
|
||||
db %00000000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6A: j
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $6B: k
|
||||
db %01100000
|
||||
db %01100100
|
||||
db %01101000
|
||||
db %01111000
|
||||
db %01100100
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6C: l
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6D: m
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01010100
|
||||
db %01101010
|
||||
db %01101010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6E: n
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6F: o
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $70: p
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
|
||||
// $71: q
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00110100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111100
|
||||
db %00001110
|
||||
db %00001100
|
||||
|
||||
// $72: r
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $73: s
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %00011000
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $74: t
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %01111000
|
||||
db %00110000
|
||||
db %00110010
|
||||
db %00011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $75: u
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $76: v
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $77: w
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %00101100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $78: x
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $79: y
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $7A: z
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $7B: Opening curly bracket "{"
|
||||
db %00011100
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011100
|
||||
|
||||
// $7C: Vertical line "|"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
|
||||
// $7D: Closing curly bracket "{"
|
||||
db %00111000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111000
|
||||
|
||||
// $7E: Tilde "~"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01110000
|
||||
db %01011010
|
||||
db %00001110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
507
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/LIB/SNES.INC
Normal file
507
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/LIB/SNES.INC
Normal file
@ -0,0 +1,507 @@
|
||||
//============== (Key: R=Read, W=Write, D=Double Read/Write)
|
||||
// SNES Include
|
||||
//==============
|
||||
// Memory Map
|
||||
constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW
|
||||
|
||||
// PPU Picture Processing Unit Ports (Write-Only)
|
||||
constant REG_INIDISP($2100) // Display Control 1 1B/W
|
||||
constant REG_OBSEL($2101) // Object Size & Object Base 1B/W
|
||||
constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W
|
||||
constant REG_OAMDATA($2104) // OAM Data Write 1B/W D
|
||||
constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W
|
||||
constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W
|
||||
constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W
|
||||
constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W
|
||||
constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D
|
||||
constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D
|
||||
constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W
|
||||
constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W
|
||||
constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W
|
||||
constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W
|
||||
constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W
|
||||
constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D
|
||||
constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D
|
||||
constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D
|
||||
constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D
|
||||
constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D
|
||||
constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D
|
||||
constant REG_CGADD($2121) // Palette CGRAM Address 1B/W
|
||||
constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D
|
||||
constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W
|
||||
constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W
|
||||
constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W
|
||||
constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W
|
||||
constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W
|
||||
constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W
|
||||
constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W
|
||||
constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W
|
||||
constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W
|
||||
constant REG_TM($212C) // Main Screen Designation 1B/W
|
||||
constant REG_TS($212D) // Sub Screen Designation 1B/W
|
||||
constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W
|
||||
constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W
|
||||
constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W
|
||||
constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W
|
||||
constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W
|
||||
constant REG_SETINI($2133) // Display Control 2 1B/W
|
||||
|
||||
// PPU Picture Processing Unit Ports (Read-Only)
|
||||
constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R
|
||||
constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R
|
||||
constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R
|
||||
constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R
|
||||
constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D
|
||||
constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R
|
||||
constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R
|
||||
constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D
|
||||
constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D
|
||||
constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D
|
||||
constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R
|
||||
constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R
|
||||
|
||||
// APU Audio Processing Unit Ports (Read/Write)
|
||||
constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW
|
||||
constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW
|
||||
constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW
|
||||
constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW
|
||||
// $2140..$2143 - APU Ports Mirrored To $2144..$217F
|
||||
|
||||
// WRAM Access Ports
|
||||
constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW
|
||||
constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W
|
||||
constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W
|
||||
constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W
|
||||
// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus)
|
||||
// $2200..$3FFF - Unused Region (A-Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz)
|
||||
// ($4000..$4015 - Unused Region (Open Bus)
|
||||
constant REG_JOYWR($4016) // Joypad Output 1B/W
|
||||
constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R
|
||||
constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R
|
||||
// $4018..$41FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Write-only, Read=Open Bus)
|
||||
constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W
|
||||
constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W
|
||||
constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W
|
||||
constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W
|
||||
constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W
|
||||
constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W
|
||||
constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W
|
||||
constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W
|
||||
constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W
|
||||
constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W
|
||||
constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W
|
||||
constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W
|
||||
// $420E..$420F - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Read-only)
|
||||
constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R
|
||||
constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R
|
||||
constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R
|
||||
constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R
|
||||
constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R
|
||||
constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R
|
||||
constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R
|
||||
constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R
|
||||
// $4220..$42FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port)
|
||||
constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW
|
||||
// $430C..$430E - Unused Region (Open Bus)
|
||||
constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW
|
||||
|
||||
constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW
|
||||
// $431C..$431E - Unused Region (Open Bus)
|
||||
constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW
|
||||
|
||||
constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW
|
||||
// $432C..$432E - Unused Region (Open Bus)
|
||||
constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW
|
||||
|
||||
constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW
|
||||
// $433C..$433E - Unused Region (Open Bus)
|
||||
constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW
|
||||
|
||||
constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW
|
||||
// $434C..$434E - Unused Region (Open Bus)
|
||||
constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW
|
||||
|
||||
constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW
|
||||
// $435C..$435E - Unused Region (Open Bus)
|
||||
constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW
|
||||
|
||||
constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW
|
||||
// $436C..$436E - Unused Region (Open Bus)
|
||||
constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW
|
||||
|
||||
constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW
|
||||
// $437C..$437E - Unused Region (Open Bus)
|
||||
constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW
|
||||
// $4380..$5FFF - Unused Region (Open Bus)
|
||||
|
||||
// Further Memory
|
||||
// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges)
|
||||
// $8000..$FFFF - Cartridge ROM
|
||||
|
||||
//================================================
|
||||
// ReadD16 - Read Double 8-bit To Memory (16-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro ReadD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} // Load Source High Byte
|
||||
sta {DEST} + 1 // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// ReadD16Index - Read Double 8-bit To Index (16-Bit)
|
||||
//====================================================
|
||||
// SRC: Source Address
|
||||
// REG: Destination Index Register (x, y)
|
||||
macro ReadD16Index(SRC, REG) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
lda {SRC} // Load Source High Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
ta{REG} // Transfer 16-Bit A To 16-Bit REG
|
||||
}
|
||||
|
||||
//================================================
|
||||
// WriteD8 - Write Memory To Double 8-bit (8-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD8(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//==================================================
|
||||
// WriteD16 - Write Memory To Double 8-bit (16-Bit)
|
||||
//==================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} + 1 // Load Source High Byte
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// WriteD8Index - Write Index To Double 8-bit (8-Bit)
|
||||
//====================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD8Index(REG, DEST) {
|
||||
t{REG}a // Transfer 8-Bit REG To 8-Bit A
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//======================================================
|
||||
// WriteD16Index - Write Index To Double 8-bit (16-Bit)
|
||||
//======================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD16Index(REG, DEST) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Transfer 16-Bit REG To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//=====================
|
||||
// SNES Initialisation
|
||||
//=====================
|
||||
// ROMSPEED: ROM Speed (SLOWROM, FASTROM)
|
||||
constant SLOWROM(0) // Access Cycle Designation (Slow ROM)
|
||||
constant FASTROM(1) // Access Cycle Designation (Fast ROM)
|
||||
macro SNES_INIT(ROMSPEED) {
|
||||
sei // Disable Interrupts
|
||||
clc // Clear Carry To Switch To Native Mode
|
||||
xce // Xchange Carry & Emulation Bit (Native Mode)
|
||||
|
||||
phk
|
||||
plb
|
||||
rep #$38
|
||||
|
||||
ldx.w #$1FFF // Set Stack To $1FFF
|
||||
txs // Transfer Index Register X To Stack Pointer
|
||||
|
||||
lda.w #$0000
|
||||
tcd
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
|
||||
lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1
|
||||
sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM)
|
||||
|
||||
lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness)
|
||||
sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100)
|
||||
|
||||
stz.w REG_OBSEL // Object Size & Object Base ($2101)
|
||||
stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102)
|
||||
stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103)
|
||||
stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105)
|
||||
stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106)
|
||||
stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107)
|
||||
stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108)
|
||||
stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109)
|
||||
stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A)
|
||||
stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B)
|
||||
stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114)
|
||||
|
||||
lda.b #$01
|
||||
stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B)
|
||||
sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D)
|
||||
stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E)
|
||||
sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120)
|
||||
|
||||
stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123)
|
||||
stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124)
|
||||
stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125)
|
||||
stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126)
|
||||
stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127)
|
||||
stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128)
|
||||
stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129)
|
||||
stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A)
|
||||
stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B)
|
||||
stz.w REG_TM // Main Screen Designation = 0 ($212C)
|
||||
stz.w REG_TS // Sub Screen Designation = 0 ($212D)
|
||||
stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E)
|
||||
stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F)
|
||||
|
||||
lda.b #$30
|
||||
sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130)
|
||||
stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131)
|
||||
|
||||
lda.b #$E0
|
||||
sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132)
|
||||
stz.w REG_SETINI // Display Control 2 = 0 ($2133)
|
||||
|
||||
stz.w REG_JOYWR // Joypad Output = 0 ($4016)
|
||||
|
||||
stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200)
|
||||
|
||||
lda.b #$FF
|
||||
sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201)
|
||||
|
||||
stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202)
|
||||
stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203)
|
||||
stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204)
|
||||
stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205)
|
||||
stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206)
|
||||
stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207)
|
||||
stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208)
|
||||
stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209)
|
||||
stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A)
|
||||
stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B)
|
||||
stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C)
|
||||
|
||||
// Clear OAM
|
||||
ldx.w #$0080
|
||||
lda.b #$E0
|
||||
-
|
||||
sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104)
|
||||
sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
ldx.w #$0020
|
||||
-
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
// Clear WRAM
|
||||
ldy.w #$0000
|
||||
sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181)
|
||||
stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183)
|
||||
|
||||
ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom
|
||||
lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank)
|
||||
stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302)
|
||||
sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
nop // Delay
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B)
|
||||
|
||||
// VRAM
|
||||
lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119)
|
||||
sta.w REG_VMAIN // VRAM Address Increment Mode ($2115)
|
||||
ldy.w #$0000
|
||||
sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
// CGRAM
|
||||
stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121)
|
||||
ldx.w #$200 // 512 Byte
|
||||
stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305)
|
||||
ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
jml +
|
||||
|
||||
CONST_ZERO:
|
||||
dw $0000
|
||||
|
||||
+
|
||||
}
|
||||
558
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/LIB/SNES_GFX.INC
Normal file
558
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/LIB/SNES_GFX.INC
Normal file
@ -0,0 +1,558 @@
|
||||
//===============
|
||||
// SNES Graphics
|
||||
//===============
|
||||
|
||||
//=============================
|
||||
// WaitNMI - Wait For NMI Flag
|
||||
//=============================
|
||||
macro WaitNMI() {
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
}
|
||||
|
||||
//======================================
|
||||
// WaitHV - Wait For H/V Timer IRQ Flag
|
||||
//======================================
|
||||
macro WaitHV() {
|
||||
-
|
||||
bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag
|
||||
bpl - // Wait For H/V Timer IRQ Flag
|
||||
}
|
||||
|
||||
//========================================
|
||||
// WaitHVB - Wait For V-Blank Period Flag
|
||||
//========================================
|
||||
macro WaitHVB() {
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
}
|
||||
|
||||
//================================================================
|
||||
// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing)
|
||||
//================================================================
|
||||
macro FadeIN() {
|
||||
ldx.w #$0000 // Set X To Mininmum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
inx // Increments Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$0F // Compare With Maximum Brightness Level (15)
|
||||
bne - // IF (Screen != Maximum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//=================================================================
|
||||
// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing)
|
||||
//=================================================================
|
||||
macro FadeOUT() {
|
||||
ldx.w #$000F // Set X To Maximum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
dex // Decrement Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$00 // Compare With Minimum Brightness Level
|
||||
bne - // IF (Screen != Minimum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//======================================
|
||||
// LoadPAL - Load Palette Data To CGRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadPAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==========================================
|
||||
// UpdatePAL - Update Palette Data To CGRAM
|
||||
//==========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdatePAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearLOVRAM - Clear VRAM Lo Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearHIVRAM - Clear VRAM Hi Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===================================
|
||||
// ClearVRAM - Clear VRAM Fixed Word
|
||||
//===================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
// Transfer Lo Byte
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Transfer Hi Byte
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==================================
|
||||
// LoadVRAM - Load GFX Data To VRAM
|
||||
//==================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================================
|
||||
// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride
|
||||
//========================================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// STRIDE: Dest Offset Stride
|
||||
// COUNT: Number Of DMA Transfers
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
-
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
txa // A = X
|
||||
clc // Clear Carry Flag
|
||||
adc.w #{STRIDE} >> 1
|
||||
tax // X = A
|
||||
lda.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1
|
||||
bne -
|
||||
}
|
||||
|
||||
//======================================
|
||||
// UpdateVRAM - Update GFX Data To VRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdateVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===========================================
|
||||
// LoadM7VRAM - Load Mode 7 GFX Data To VRAM
|
||||
//===========================================
|
||||
// SRCMAP: 24-Bit Address Of Source Map Data
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZEMAP: Size Of Map Data (BYTE Size)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) {
|
||||
// Load Mode7 Map Data To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCMAP} // Set Source Offset (Map)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCMAP} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map)
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset (Tiles)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8 - Scroll GFX BG From Memory (8-Bit)
|
||||
//===============================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8(BGSCR, BGPOS, DIR) {
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16 - Scroll GFX BG From Memory (16-Bit)
|
||||
//=================================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16(BGSCR, BGPOS, DIR) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
lda {BGSCR} + 1 // Load BG Scroll Position High Byte
|
||||
sta {BGPOS} // Store BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8I - Scroll GFX BG From Index (8-Bit)
|
||||
//===============================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
t{REG}a // Swaps 8-Bit Index To 8-Bit A
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16I - Scroll GFX BG From Index (16-Bit)
|
||||
//=================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Word
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Swaps 16-Bit Index To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {BGPOS} // Store A To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//======================================
|
||||
// Mode7CALC - Mode7 Matrix Calculation
|
||||
//======================================
|
||||
// A: Mode7 COS A Word
|
||||
// B: Mode7 SIN A Word
|
||||
// C: Mode7 SIN B Word
|
||||
// D: Mode7 COS B Word
|
||||
// ANGLE: Mode7 Angle Byte
|
||||
// SX: Mode7 Scale X Word
|
||||
// SY: Mode7 Scale Y Word
|
||||
// SINCOS: Mode7 SINCOS Table
|
||||
macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) {
|
||||
lda.b {ANGLE} // Load Angle To A
|
||||
tax // Transfer A To X
|
||||
|
||||
// Calculate B & C (SIN)
|
||||
// B
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {B}
|
||||
// C
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1 // High Byte
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
eor.b #$FF // Make Negative
|
||||
inc
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {C}
|
||||
|
||||
// Change X Index To Point To COS Values (X + 64)
|
||||
txa // Transfer X Index To A
|
||||
clc // Clear Carry Flag
|
||||
adc.b #64 // Add 64 With Carry
|
||||
tax // Transfer A To X Index
|
||||
|
||||
// Calculate A & D (COS)
|
||||
// A
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {A}
|
||||
// D
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {D}
|
||||
|
||||
// Store Result To Matrix
|
||||
lda.b {A}
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {A} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
|
||||
lda.b {B}
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
lda.b {B} + 1
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
|
||||
lda.b {C}
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
lda.b {C} + 1
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
|
||||
lda.b {D}
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
lda.b {D} + 1
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
//=============
|
||||
// SNES Header
|
||||
//=============
|
||||
seek($FFC0)
|
||||
// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes)
|
||||
db "65816 CPU TEST ADC "
|
||||
// "123456789012345678901"
|
||||
|
||||
// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode)
|
||||
db $20
|
||||
// ||___________________Map Mode:
|
||||
// | $X0 = LoROM/32K Banks (Mode 20)
|
||||
// | $X1 = HiROM/64K Banks (Mode 21)
|
||||
// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable)
|
||||
// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable)
|
||||
// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM)
|
||||
// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable)
|
||||
|
||||
// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type)
|
||||
db $00
|
||||
// ||___________________Type:
|
||||
// | $00 = ROM
|
||||
// | $01 = ROM+RAM
|
||||
// Co-processor: $02 = ROM+RAM+Battery
|
||||
// $0X = DSP $X3 = ROM+Co-processor
|
||||
// $1X = GSU $X4 = ROM+Co-processor+RAM
|
||||
// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery
|
||||
// $3X = SA-1 $X6 = ROM+Co-processor+Battery
|
||||
// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513
|
||||
// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked
|
||||
|
||||
// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits)
|
||||
db $01
|
||||
// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit)
|
||||
// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit)
|
||||
// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit)
|
||||
// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit)
|
||||
// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit)
|
||||
// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit)
|
||||
|
||||
// RAM SIZE
|
||||
db $00
|
||||
// $00 = None, $04 = 16Kb
|
||||
// $01 = 2Kb, $05 = 32Kb
|
||||
// $02 = 4Kb, $06 = 64Kb
|
||||
// $03 = 8Kb, $07 = 128Kb
|
||||
|
||||
// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz)
|
||||
db $00
|
||||
// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL)
|
||||
// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL)
|
||||
// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL)
|
||||
// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL)
|
||||
// $04 = Finland (PAL), $0D = South (K)orea (NTSC)
|
||||
// $05 = Denmark (PAL), $0E = (A)Common (ANY)
|
||||
// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC)
|
||||
// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M)
|
||||
// $08 = (S)pain (PAL), $11 = (U)Australia (PAL)
|
||||
|
||||
// DEVELOPER ID CODE
|
||||
db $00
|
||||
// $00 = None
|
||||
// $01 = Nintendo
|
||||
// $33 = New (Uses Extended Header)
|
||||
|
||||
// ROM VERSION NUMBER
|
||||
db $00
|
||||
// $00 = 1.00, $01 = 1.01
|
||||
|
||||
// COMPLEMENT CHECK
|
||||
db "CC"
|
||||
// CHECKSUM
|
||||
db "CS"
|
||||
|
||||
// NATIVE VECTOR (65C816 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (BRK Opcode)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $0000 // RESET VECTOR (Unused)
|
||||
dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt)
|
||||
|
||||
// EMU VECTOR (6502 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (Unused)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET)
|
||||
dw $0000 // IRQ/BRK VECTOR
|
||||
1
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/make.bat
Normal file
1
OSBindings/Mac/Clock SignalTests/krom 65816/ADC/make.bat
Normal file
@ -0,0 +1 @@
|
||||
bass CPUADC.asm
|
||||
2772
OSBindings/Mac/Clock SignalTests/krom 65816/AND/CPUAND.asm
Normal file
2772
OSBindings/Mac/Clock SignalTests/krom 65816/AND/CPUAND.asm
Normal file
File diff suppressed because it is too large
Load Diff
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/AND/CPUAND.png
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/AND/CPUAND.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.0 KiB |
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/AND/CPUAND.sfc
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/AND/CPUAND.sfc
Normal file
Binary file not shown.
957
OSBindings/Mac/Clock SignalTests/krom 65816/AND/Font8x8.asm
Normal file
957
OSBindings/Mac/Clock SignalTests/krom 65816/AND/Font8x8.asm
Normal file
@ -0,0 +1,957 @@
|
||||
fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes
|
||||
|
||||
// $20: Space " "
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $21: Exclamation mark "!"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $22: Quotation mark """
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $23: Cross hatch "#"
|
||||
db %00010100
|
||||
db %00010100
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $24: Dollar sign "$"
|
||||
db %00111100
|
||||
db %01101010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01010110
|
||||
db %00111100
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $25: Percent sign "%"
|
||||
db %00100010
|
||||
db %01010100
|
||||
db %00101000
|
||||
db %00010100
|
||||
db %00101010
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $26: Ampersand "&"
|
||||
db %00110000
|
||||
db %01001000
|
||||
db %00110010
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00110010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $27: Closing single quote "'"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $28: Opening parentheses "("
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
|
||||
// $29: Closing parentheses ")"
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
|
||||
// $2A: Asterisk "*"
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2B: Plus "+"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2C: Comma ","
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $2D: Hyphen "-"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2E: Period "."
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2F: Forward slash "/"
|
||||
db %00000010
|
||||
db %00000110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01100000
|
||||
db %01000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $30: 0
|
||||
db %00111010
|
||||
db %01100100
|
||||
db %01001010
|
||||
db %01010010
|
||||
db %00100110
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $31: 1
|
||||
db %00011000
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $32: 2
|
||||
db %00111000
|
||||
db %01001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $33: 3
|
||||
db %00111100
|
||||
db %01000110
|
||||
db %00011100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $34: 4
|
||||
db %00001100
|
||||
db %00011100
|
||||
db %00101100
|
||||
db %01001100
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $35: 5
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $36: 6
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $37: 7
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $38: 8
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $39: 9
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %00000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $3A: Colon ":"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3B: Semicolon ";"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $3C: Less than sign "<"
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3D: Equals sign "="
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3E: Greater than sign ">"
|
||||
db %00000000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3F: Question mark "?"
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
|
||||
// $40: At sign "@"
|
||||
db %01111100
|
||||
db %10000010
|
||||
db %10111010
|
||||
db %10101010
|
||||
db %10111110
|
||||
db %01000000
|
||||
db %00111110
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $41: A
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00100100
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $42: B
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $43: C
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $44: D
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $45: E
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $46: F
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $47: G
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $48: H
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $49: I
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4A: J
|
||||
db %00111110
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %01001100
|
||||
db %01111100
|
||||
db %00111000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4B: K
|
||||
db %01100110
|
||||
db %01101100
|
||||
db %01111000
|
||||
db %01111000
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4C: L
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4D: M
|
||||
db %01000010
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4E: N
|
||||
db %01000110
|
||||
db %01100110
|
||||
db %01110110
|
||||
db %01111110
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4F: O
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $50: P
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $51: Q
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100010
|
||||
db %01101010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $52: R
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $53: S
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $54: T
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $55: U
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $56: V
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00100100
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $57: W
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $58: X
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $59: Y
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5A: Z
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $5B: Opening square bracket "["
|
||||
db %00011100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011100
|
||||
|
||||
// $5C: Back slash "\"
|
||||
db %01000000
|
||||
db %01100000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00000110
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $5D: Closing square bracket "]"
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111000
|
||||
|
||||
// $5E: Caret "^"
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5F: Underscore "_"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %11111111
|
||||
|
||||
// $60: Opening single quote "`"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $61: a
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01100100
|
||||
db %01100100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $62: b
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00111100
|
||||
db %00110010
|
||||
db %00110010
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $63: c
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $64: d
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $65: e
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01101000
|
||||
db %01110010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $66: f
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011100
|
||||
db %00110010
|
||||
db %00110000
|
||||
db %01111100
|
||||
db %00110000
|
||||
db %00110000
|
||||
|
||||
// $67: g
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111010
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $68: h
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $69: i
|
||||
db %00110000
|
||||
db %00000000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6A: j
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $6B: k
|
||||
db %01100000
|
||||
db %01100100
|
||||
db %01101000
|
||||
db %01111000
|
||||
db %01100100
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6C: l
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6D: m
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01010100
|
||||
db %01101010
|
||||
db %01101010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6E: n
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6F: o
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $70: p
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
|
||||
// $71: q
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00110100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111100
|
||||
db %00001110
|
||||
db %00001100
|
||||
|
||||
// $72: r
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $73: s
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %00011000
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $74: t
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %01111000
|
||||
db %00110000
|
||||
db %00110010
|
||||
db %00011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $75: u
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $76: v
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $77: w
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %00101100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $78: x
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $79: y
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $7A: z
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $7B: Opening curly bracket "{"
|
||||
db %00011100
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011100
|
||||
|
||||
// $7C: Vertical line "|"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
|
||||
// $7D: Closing curly bracket "{"
|
||||
db %00111000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111000
|
||||
|
||||
// $7E: Tilde "~"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01110000
|
||||
db %01011010
|
||||
db %00001110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
507
OSBindings/Mac/Clock SignalTests/krom 65816/AND/LIB/SNES.INC
Normal file
507
OSBindings/Mac/Clock SignalTests/krom 65816/AND/LIB/SNES.INC
Normal file
@ -0,0 +1,507 @@
|
||||
//============== (Key: R=Read, W=Write, D=Double Read/Write)
|
||||
// SNES Include
|
||||
//==============
|
||||
// Memory Map
|
||||
constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW
|
||||
|
||||
// PPU Picture Processing Unit Ports (Write-Only)
|
||||
constant REG_INIDISP($2100) // Display Control 1 1B/W
|
||||
constant REG_OBSEL($2101) // Object Size & Object Base 1B/W
|
||||
constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W
|
||||
constant REG_OAMDATA($2104) // OAM Data Write 1B/W D
|
||||
constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W
|
||||
constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W
|
||||
constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W
|
||||
constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W
|
||||
constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D
|
||||
constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D
|
||||
constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W
|
||||
constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W
|
||||
constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W
|
||||
constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W
|
||||
constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W
|
||||
constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D
|
||||
constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D
|
||||
constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D
|
||||
constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D
|
||||
constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D
|
||||
constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D
|
||||
constant REG_CGADD($2121) // Palette CGRAM Address 1B/W
|
||||
constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D
|
||||
constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W
|
||||
constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W
|
||||
constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W
|
||||
constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W
|
||||
constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W
|
||||
constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W
|
||||
constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W
|
||||
constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W
|
||||
constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W
|
||||
constant REG_TM($212C) // Main Screen Designation 1B/W
|
||||
constant REG_TS($212D) // Sub Screen Designation 1B/W
|
||||
constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W
|
||||
constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W
|
||||
constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W
|
||||
constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W
|
||||
constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W
|
||||
constant REG_SETINI($2133) // Display Control 2 1B/W
|
||||
|
||||
// PPU Picture Processing Unit Ports (Read-Only)
|
||||
constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R
|
||||
constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R
|
||||
constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R
|
||||
constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R
|
||||
constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D
|
||||
constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R
|
||||
constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R
|
||||
constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D
|
||||
constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D
|
||||
constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D
|
||||
constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R
|
||||
constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R
|
||||
|
||||
// APU Audio Processing Unit Ports (Read/Write)
|
||||
constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW
|
||||
constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW
|
||||
constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW
|
||||
constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW
|
||||
// $2140..$2143 - APU Ports Mirrored To $2144..$217F
|
||||
|
||||
// WRAM Access Ports
|
||||
constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW
|
||||
constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W
|
||||
constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W
|
||||
constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W
|
||||
// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus)
|
||||
// $2200..$3FFF - Unused Region (A-Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz)
|
||||
// ($4000..$4015 - Unused Region (Open Bus)
|
||||
constant REG_JOYWR($4016) // Joypad Output 1B/W
|
||||
constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R
|
||||
constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R
|
||||
// $4018..$41FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Write-only, Read=Open Bus)
|
||||
constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W
|
||||
constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W
|
||||
constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W
|
||||
constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W
|
||||
constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W
|
||||
constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W
|
||||
constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W
|
||||
constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W
|
||||
constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W
|
||||
constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W
|
||||
constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W
|
||||
constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W
|
||||
// $420E..$420F - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Read-only)
|
||||
constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R
|
||||
constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R
|
||||
constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R
|
||||
constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R
|
||||
constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R
|
||||
constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R
|
||||
constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R
|
||||
constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R
|
||||
// $4220..$42FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port)
|
||||
constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW
|
||||
// $430C..$430E - Unused Region (Open Bus)
|
||||
constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW
|
||||
|
||||
constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW
|
||||
// $431C..$431E - Unused Region (Open Bus)
|
||||
constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW
|
||||
|
||||
constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW
|
||||
// $432C..$432E - Unused Region (Open Bus)
|
||||
constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW
|
||||
|
||||
constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW
|
||||
// $433C..$433E - Unused Region (Open Bus)
|
||||
constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW
|
||||
|
||||
constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW
|
||||
// $434C..$434E - Unused Region (Open Bus)
|
||||
constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW
|
||||
|
||||
constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW
|
||||
// $435C..$435E - Unused Region (Open Bus)
|
||||
constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW
|
||||
|
||||
constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW
|
||||
// $436C..$436E - Unused Region (Open Bus)
|
||||
constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW
|
||||
|
||||
constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW
|
||||
// $437C..$437E - Unused Region (Open Bus)
|
||||
constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW
|
||||
// $4380..$5FFF - Unused Region (Open Bus)
|
||||
|
||||
// Further Memory
|
||||
// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges)
|
||||
// $8000..$FFFF - Cartridge ROM
|
||||
|
||||
//================================================
|
||||
// ReadD16 - Read Double 8-bit To Memory (16-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro ReadD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} // Load Source High Byte
|
||||
sta {DEST} + 1 // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// ReadD16Index - Read Double 8-bit To Index (16-Bit)
|
||||
//====================================================
|
||||
// SRC: Source Address
|
||||
// REG: Destination Index Register (x, y)
|
||||
macro ReadD16Index(SRC, REG) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
lda {SRC} // Load Source High Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
ta{REG} // Transfer 16-Bit A To 16-Bit REG
|
||||
}
|
||||
|
||||
//================================================
|
||||
// WriteD8 - Write Memory To Double 8-bit (8-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD8(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//==================================================
|
||||
// WriteD16 - Write Memory To Double 8-bit (16-Bit)
|
||||
//==================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} + 1 // Load Source High Byte
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// WriteD8Index - Write Index To Double 8-bit (8-Bit)
|
||||
//====================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD8Index(REG, DEST) {
|
||||
t{REG}a // Transfer 8-Bit REG To 8-Bit A
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//======================================================
|
||||
// WriteD16Index - Write Index To Double 8-bit (16-Bit)
|
||||
//======================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD16Index(REG, DEST) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Transfer 16-Bit REG To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//=====================
|
||||
// SNES Initialisation
|
||||
//=====================
|
||||
// ROMSPEED: ROM Speed (SLOWROM, FASTROM)
|
||||
constant SLOWROM(0) // Access Cycle Designation (Slow ROM)
|
||||
constant FASTROM(1) // Access Cycle Designation (Fast ROM)
|
||||
macro SNES_INIT(ROMSPEED) {
|
||||
sei // Disable Interrupts
|
||||
clc // Clear Carry To Switch To Native Mode
|
||||
xce // Xchange Carry & Emulation Bit (Native Mode)
|
||||
|
||||
phk
|
||||
plb
|
||||
rep #$38
|
||||
|
||||
ldx.w #$1FFF // Set Stack To $1FFF
|
||||
txs // Transfer Index Register X To Stack Pointer
|
||||
|
||||
lda.w #$0000
|
||||
tcd
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
|
||||
lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1
|
||||
sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM)
|
||||
|
||||
lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness)
|
||||
sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100)
|
||||
|
||||
stz.w REG_OBSEL // Object Size & Object Base ($2101)
|
||||
stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102)
|
||||
stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103)
|
||||
stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105)
|
||||
stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106)
|
||||
stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107)
|
||||
stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108)
|
||||
stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109)
|
||||
stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A)
|
||||
stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B)
|
||||
stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114)
|
||||
|
||||
lda.b #$01
|
||||
stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B)
|
||||
sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D)
|
||||
stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E)
|
||||
sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120)
|
||||
|
||||
stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123)
|
||||
stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124)
|
||||
stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125)
|
||||
stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126)
|
||||
stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127)
|
||||
stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128)
|
||||
stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129)
|
||||
stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A)
|
||||
stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B)
|
||||
stz.w REG_TM // Main Screen Designation = 0 ($212C)
|
||||
stz.w REG_TS // Sub Screen Designation = 0 ($212D)
|
||||
stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E)
|
||||
stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F)
|
||||
|
||||
lda.b #$30
|
||||
sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130)
|
||||
stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131)
|
||||
|
||||
lda.b #$E0
|
||||
sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132)
|
||||
stz.w REG_SETINI // Display Control 2 = 0 ($2133)
|
||||
|
||||
stz.w REG_JOYWR // Joypad Output = 0 ($4016)
|
||||
|
||||
stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200)
|
||||
|
||||
lda.b #$FF
|
||||
sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201)
|
||||
|
||||
stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202)
|
||||
stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203)
|
||||
stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204)
|
||||
stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205)
|
||||
stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206)
|
||||
stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207)
|
||||
stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208)
|
||||
stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209)
|
||||
stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A)
|
||||
stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B)
|
||||
stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C)
|
||||
|
||||
// Clear OAM
|
||||
ldx.w #$0080
|
||||
lda.b #$E0
|
||||
-
|
||||
sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104)
|
||||
sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
ldx.w #$0020
|
||||
-
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
// Clear WRAM
|
||||
ldy.w #$0000
|
||||
sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181)
|
||||
stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183)
|
||||
|
||||
ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom
|
||||
lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank)
|
||||
stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302)
|
||||
sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
nop // Delay
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B)
|
||||
|
||||
// VRAM
|
||||
lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119)
|
||||
sta.w REG_VMAIN // VRAM Address Increment Mode ($2115)
|
||||
ldy.w #$0000
|
||||
sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
// CGRAM
|
||||
stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121)
|
||||
ldx.w #$200 // 512 Byte
|
||||
stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305)
|
||||
ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
jml +
|
||||
|
||||
CONST_ZERO:
|
||||
dw $0000
|
||||
|
||||
+
|
||||
}
|
||||
558
OSBindings/Mac/Clock SignalTests/krom 65816/AND/LIB/SNES_GFX.INC
Normal file
558
OSBindings/Mac/Clock SignalTests/krom 65816/AND/LIB/SNES_GFX.INC
Normal file
@ -0,0 +1,558 @@
|
||||
//===============
|
||||
// SNES Graphics
|
||||
//===============
|
||||
|
||||
//=============================
|
||||
// WaitNMI - Wait For NMI Flag
|
||||
//=============================
|
||||
macro WaitNMI() {
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
}
|
||||
|
||||
//======================================
|
||||
// WaitHV - Wait For H/V Timer IRQ Flag
|
||||
//======================================
|
||||
macro WaitHV() {
|
||||
-
|
||||
bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag
|
||||
bpl - // Wait For H/V Timer IRQ Flag
|
||||
}
|
||||
|
||||
//========================================
|
||||
// WaitHVB - Wait For V-Blank Period Flag
|
||||
//========================================
|
||||
macro WaitHVB() {
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
}
|
||||
|
||||
//================================================================
|
||||
// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing)
|
||||
//================================================================
|
||||
macro FadeIN() {
|
||||
ldx.w #$0000 // Set X To Mininmum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
inx // Increments Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$0F // Compare With Maximum Brightness Level (15)
|
||||
bne - // IF (Screen != Maximum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//=================================================================
|
||||
// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing)
|
||||
//=================================================================
|
||||
macro FadeOUT() {
|
||||
ldx.w #$000F // Set X To Maximum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
dex // Decrement Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$00 // Compare With Minimum Brightness Level
|
||||
bne - // IF (Screen != Minimum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//======================================
|
||||
// LoadPAL - Load Palette Data To CGRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadPAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==========================================
|
||||
// UpdatePAL - Update Palette Data To CGRAM
|
||||
//==========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdatePAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearLOVRAM - Clear VRAM Lo Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearHIVRAM - Clear VRAM Hi Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===================================
|
||||
// ClearVRAM - Clear VRAM Fixed Word
|
||||
//===================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
// Transfer Lo Byte
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Transfer Hi Byte
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==================================
|
||||
// LoadVRAM - Load GFX Data To VRAM
|
||||
//==================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================================
|
||||
// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride
|
||||
//========================================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// STRIDE: Dest Offset Stride
|
||||
// COUNT: Number Of DMA Transfers
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
-
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
txa // A = X
|
||||
clc // Clear Carry Flag
|
||||
adc.w #{STRIDE} >> 1
|
||||
tax // X = A
|
||||
lda.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1
|
||||
bne -
|
||||
}
|
||||
|
||||
//======================================
|
||||
// UpdateVRAM - Update GFX Data To VRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdateVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===========================================
|
||||
// LoadM7VRAM - Load Mode 7 GFX Data To VRAM
|
||||
//===========================================
|
||||
// SRCMAP: 24-Bit Address Of Source Map Data
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZEMAP: Size Of Map Data (BYTE Size)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) {
|
||||
// Load Mode7 Map Data To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCMAP} // Set Source Offset (Map)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCMAP} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map)
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset (Tiles)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8 - Scroll GFX BG From Memory (8-Bit)
|
||||
//===============================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8(BGSCR, BGPOS, DIR) {
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16 - Scroll GFX BG From Memory (16-Bit)
|
||||
//=================================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16(BGSCR, BGPOS, DIR) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
lda {BGSCR} + 1 // Load BG Scroll Position High Byte
|
||||
sta {BGPOS} // Store BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8I - Scroll GFX BG From Index (8-Bit)
|
||||
//===============================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
t{REG}a // Swaps 8-Bit Index To 8-Bit A
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16I - Scroll GFX BG From Index (16-Bit)
|
||||
//=================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Word
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Swaps 16-Bit Index To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {BGPOS} // Store A To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//======================================
|
||||
// Mode7CALC - Mode7 Matrix Calculation
|
||||
//======================================
|
||||
// A: Mode7 COS A Word
|
||||
// B: Mode7 SIN A Word
|
||||
// C: Mode7 SIN B Word
|
||||
// D: Mode7 COS B Word
|
||||
// ANGLE: Mode7 Angle Byte
|
||||
// SX: Mode7 Scale X Word
|
||||
// SY: Mode7 Scale Y Word
|
||||
// SINCOS: Mode7 SINCOS Table
|
||||
macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) {
|
||||
lda.b {ANGLE} // Load Angle To A
|
||||
tax // Transfer A To X
|
||||
|
||||
// Calculate B & C (SIN)
|
||||
// B
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {B}
|
||||
// C
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1 // High Byte
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
eor.b #$FF // Make Negative
|
||||
inc
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {C}
|
||||
|
||||
// Change X Index To Point To COS Values (X + 64)
|
||||
txa // Transfer X Index To A
|
||||
clc // Clear Carry Flag
|
||||
adc.b #64 // Add 64 With Carry
|
||||
tax // Transfer A To X Index
|
||||
|
||||
// Calculate A & D (COS)
|
||||
// A
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {A}
|
||||
// D
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {D}
|
||||
|
||||
// Store Result To Matrix
|
||||
lda.b {A}
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {A} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
|
||||
lda.b {B}
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
lda.b {B} + 1
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
|
||||
lda.b {C}
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
lda.b {C} + 1
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
|
||||
lda.b {D}
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
lda.b {D} + 1
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
//=============
|
||||
// SNES Header
|
||||
//=============
|
||||
seek($FFC0)
|
||||
// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes)
|
||||
db "65816 CPU TEST AND "
|
||||
// "123456789012345678901"
|
||||
|
||||
// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode)
|
||||
db $20
|
||||
// ||___________________Map Mode:
|
||||
// | $X0 = LoROM/32K Banks (Mode 20)
|
||||
// | $X1 = HiROM/64K Banks (Mode 21)
|
||||
// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable)
|
||||
// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable)
|
||||
// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM)
|
||||
// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable)
|
||||
|
||||
// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type)
|
||||
db $00
|
||||
// ||___________________Type:
|
||||
// | $00 = ROM
|
||||
// | $01 = ROM+RAM
|
||||
// Co-processor: $02 = ROM+RAM+Battery
|
||||
// $0X = DSP $X3 = ROM+Co-processor
|
||||
// $1X = GSU $X4 = ROM+Co-processor+RAM
|
||||
// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery
|
||||
// $3X = SA-1 $X6 = ROM+Co-processor+Battery
|
||||
// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513
|
||||
// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked
|
||||
|
||||
// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits)
|
||||
db $01
|
||||
// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit)
|
||||
// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit)
|
||||
// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit)
|
||||
// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit)
|
||||
// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit)
|
||||
// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit)
|
||||
|
||||
// RAM SIZE
|
||||
db $00
|
||||
// $00 = None, $04 = 16Kb
|
||||
// $01 = 2Kb, $05 = 32Kb
|
||||
// $02 = 4Kb, $06 = 64Kb
|
||||
// $03 = 8Kb, $07 = 128Kb
|
||||
|
||||
// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz)
|
||||
db $00
|
||||
// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL)
|
||||
// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL)
|
||||
// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL)
|
||||
// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL)
|
||||
// $04 = Finland (PAL), $0D = South (K)orea (NTSC)
|
||||
// $05 = Denmark (PAL), $0E = (A)Common (ANY)
|
||||
// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC)
|
||||
// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M)
|
||||
// $08 = (S)pain (PAL), $11 = (U)Australia (PAL)
|
||||
|
||||
// DEVELOPER ID CODE
|
||||
db $00
|
||||
// $00 = None
|
||||
// $01 = Nintendo
|
||||
// $33 = New (Uses Extended Header)
|
||||
|
||||
// ROM VERSION NUMBER
|
||||
db $00
|
||||
// $00 = 1.00, $01 = 1.01
|
||||
|
||||
// COMPLEMENT CHECK
|
||||
db "CC"
|
||||
// CHECKSUM
|
||||
db "CS"
|
||||
|
||||
// NATIVE VECTOR (65C816 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (BRK Opcode)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $0000 // RESET VECTOR (Unused)
|
||||
dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt)
|
||||
|
||||
// EMU VECTOR (6502 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (Unused)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET)
|
||||
dw $0000 // IRQ/BRK VECTOR
|
||||
1
OSBindings/Mac/Clock SignalTests/krom 65816/AND/make.bat
Normal file
1
OSBindings/Mac/Clock SignalTests/krom 65816/AND/make.bat
Normal file
@ -0,0 +1 @@
|
||||
bass CPUAND.asm
|
||||
996
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/CPUASL.asm
Normal file
996
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/CPUASL.asm
Normal file
@ -0,0 +1,996 @@
|
||||
// SNES 65816 CPU Test ASL (Arithmetic Shift Left) demo by krom (Peter Lemon):
|
||||
arch snes.cpu
|
||||
output "CPUASL.sfc", create
|
||||
|
||||
macro seek(variable offset) {
|
||||
origin ((offset & $7F0000) >> 1) | (offset & $7FFF)
|
||||
base offset
|
||||
}
|
||||
|
||||
macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
ldx.w #0 // X = 0 Number Of Text Characters To Print
|
||||
{#}LoopText:
|
||||
lda.w {SRC},x // A = Text Data
|
||||
sta.w REG_VMDATAL // Store Text To VRAM Lo Byte
|
||||
inx // X++
|
||||
cpx.w #{SIZE}
|
||||
bne {#}LoopText // IF (X != 0) Loop Text Characters
|
||||
}
|
||||
|
||||
macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM Address
|
||||
|
||||
lda.b #$24 // A = "$"
|
||||
sta.w REG_VMDATAL // Store Text To VRAM Lo Byte
|
||||
|
||||
ldx.w #{SIZE} // X = Number Of Hex Characters To Print
|
||||
|
||||
{#}LoopHEX:
|
||||
dex // X--
|
||||
ldy.w #0002 // Y = 2 (Char Count)
|
||||
|
||||
lda.w {SRC},x // A = Result Data
|
||||
lsr // A >>= 4
|
||||
lsr
|
||||
lsr
|
||||
lsr // A = Result Hi Nibble
|
||||
|
||||
{#}LoopChar:
|
||||
cmp.b #10 // Compare Hi Nibble To 9
|
||||
clc // Clear Carry Flag
|
||||
bpl {#}HexLetter
|
||||
adc.b #$30 // Add Hi Nibble To ASCII Numbers
|
||||
sta.w REG_VMDATAL // Store Text To VRAM Lo Byte
|
||||
bra {#}HexEnd
|
||||
{#}HexLetter:
|
||||
adc.b #$37 // Add Hi Nibble To ASCII Letters
|
||||
sta.w REG_VMDATAL // Store Text To VRAM Lo Byte
|
||||
{#}HexEnd:
|
||||
|
||||
lda.w {SRC},x // A = Result Data
|
||||
and.b #$F // A = Result Lo Nibble
|
||||
dey // Y--
|
||||
bne {#}LoopChar // IF (Char Count != 0) Loop Char
|
||||
|
||||
cpx.w #0 // Compare X To 0
|
||||
bne {#}LoopHEX // IF (X != 0) Loop Hex Characters
|
||||
}
|
||||
|
||||
macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM Address
|
||||
|
||||
lda.b #%10000000 // A = Negative Flag Bit
|
||||
jsr {#}PSRFlagTest // Test PSR Flag Data
|
||||
|
||||
lda.b #%01000000 // A = Overflow Flag Bit
|
||||
jsr {#}PSRFlagTest // Test PSR Flag Data
|
||||
|
||||
lda.b #%00000010 // A = Zero Flag Bit
|
||||
jsr {#}PSRFlagTest // Test PSR Flag Data
|
||||
|
||||
lda.b #%00000001 // A = Carry Flag Bit
|
||||
jsr {#}PSRFlagTest // Test PSR Flag Data
|
||||
|
||||
bra {#}PSREnd
|
||||
|
||||
{#}PSRFlagTest:
|
||||
bit.b {SRC} // Test Processor Status Flag Data Bit
|
||||
bne {#}PSRFlagSet
|
||||
lda.b #$30 // A = "0"
|
||||
sta.w REG_VMDATAL // Store Text To VRAM Lo Byte
|
||||
rts // Return From Subroutine
|
||||
{#}PSRFlagSet:
|
||||
lda.b #$31 // A = "1"
|
||||
sta.w REG_VMDATAL // Store Text To VRAM Lo Byte
|
||||
rts // Return From Subroutine
|
||||
|
||||
{#}PSREnd:
|
||||
}
|
||||
|
||||
seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes
|
||||
include "LIB/SNES.INC" // Include SNES Definitions
|
||||
include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table
|
||||
include "LIB/SNES_GFX.INC" // Include Graphics Macros
|
||||
|
||||
// Variable Data
|
||||
seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF)
|
||||
ResultData:
|
||||
dw 0 // Result Data Word
|
||||
PSRFlagData:
|
||||
db 0 // Processor Status Register Flag Data Byte
|
||||
AbsoluteData:
|
||||
dw 0 // Absolute Data Word
|
||||
|
||||
seek($8000); Start:
|
||||
SNES_INIT(SLOWROM) // Run SNES Initialisation Routine
|
||||
|
||||
LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data
|
||||
LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles)
|
||||
ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word
|
||||
|
||||
// Setup Video
|
||||
lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size
|
||||
sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles
|
||||
|
||||
// Setup BG1 256 Color Background
|
||||
lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address
|
||||
sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400)
|
||||
lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address
|
||||
sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000)
|
||||
|
||||
lda.b #%00000001 // Enable BG1
|
||||
sta.w REG_TM // $212C: BG1 To Main Screen Designation
|
||||
|
||||
stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte
|
||||
stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte
|
||||
stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte
|
||||
stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte
|
||||
|
||||
lda.b #$F // Turn On Screen, Maximum Brightness
|
||||
sta.w REG_INIDISP // $2100: Screen Display
|
||||
|
||||
WaitNMI() // Wait For VSync
|
||||
|
||||
// Print Title Text
|
||||
PrintText(Title, $F882, 26) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Print Page Break Text
|
||||
PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Print Syntax/Opcode Text
|
||||
PrintText(ASLA, $F902, 26) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Print Key Text
|
||||
PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Print Page Break Text
|
||||
PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
clv // Clear Overflow Flag
|
||||
|
||||
// Run Test
|
||||
lda.b #$80 // A = $80
|
||||
asl // A <<= 1
|
||||
|
||||
// Store Result & Processor Status Flag Data
|
||||
sta.b ResultData // Store Result To Memory
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(ResultData, $FA12, 1) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
lda.b ResultData // A = Result Data
|
||||
cmp.w ASLResultCheckA
|
||||
beq Pass1
|
||||
Fail1:
|
||||
PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail1
|
||||
Pass1:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckA
|
||||
bne Fail1
|
||||
PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.b #$7F // A = $7F
|
||||
asl // A <<= 1
|
||||
|
||||
// Store Result & Processor Status Flag Data
|
||||
sta.b ResultData // Store Result To Memory
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(ResultData, $FA52, 1) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
lda.b ResultData // A = Result Data
|
||||
cmp.w ASLResultCheckB
|
||||
beq Pass2
|
||||
Fail2:
|
||||
PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail2
|
||||
Pass2:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckB
|
||||
bne Fail2
|
||||
PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.w #$8000 // A = $8000
|
||||
asl // A <<= 1
|
||||
|
||||
// Store Result & Processor Status Flag Data
|
||||
sta.b ResultData // Store Result To Memory
|
||||
php // Push Processor Status Register To Stack
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(ResultData, $FA92, 2) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
ldx.b ResultData // X = Result Data
|
||||
cpx.w ASLResultCheckC
|
||||
beq Pass3
|
||||
Fail3:
|
||||
PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail3
|
||||
Pass3:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckC
|
||||
bne Fail3
|
||||
PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.w #$7FFF // A = $7FFF
|
||||
asl // A <<= 1
|
||||
|
||||
// Store Result & Processor Status Flag Data
|
||||
sta.b ResultData // Store Result To Memory
|
||||
php // Push Processor Status Register To Stack
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(ResultData, $FAD2, 2) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
ldx.b ResultData // X = Result Data
|
||||
cpx.w ASLResultCheckD
|
||||
beq Pass4
|
||||
Fail4:
|
||||
PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail4
|
||||
Pass4:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckD
|
||||
bne Fail4
|
||||
PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
WaitNMI() // Wait For VSync
|
||||
|
||||
ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word
|
||||
|
||||
WaitNMI() // Wait For VSync
|
||||
|
||||
// Print Syntax/Opcode Text
|
||||
PrintText(ASLAddr, $F902, 26) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
clv // Clear Overflow Flag
|
||||
|
||||
// Run Test
|
||||
lda.b #$80 // A = $80
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
asl.w AbsoluteData // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA12, 1) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
lda.b AbsoluteData // A = Result Data
|
||||
cmp.w ASLResultCheckA
|
||||
beq Pass5
|
||||
Fail5:
|
||||
PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail5
|
||||
Pass5:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckA
|
||||
bne Fail5
|
||||
PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.b #$7F // A = $7F
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
asl.w AbsoluteData // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA52, 1) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
lda.b AbsoluteData // A = Result Data
|
||||
cmp.w ASLResultCheckB
|
||||
beq Pass6
|
||||
Fail6:
|
||||
PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail6
|
||||
Pass6:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckB
|
||||
bne Fail6
|
||||
PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.w #$8000 // A = $8000
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
asl.w AbsoluteData // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA92, 2) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
ldx.b AbsoluteData // X = Result Data
|
||||
cpx.w ASLResultCheckC
|
||||
beq Pass7
|
||||
Fail7:
|
||||
PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail7
|
||||
Pass7:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckC
|
||||
bne Fail7
|
||||
PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.w #$7FFF // A = $7FFF
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
asl.w AbsoluteData // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
ldx.b AbsoluteData // X = Result Data
|
||||
cpx.w ASLResultCheckD
|
||||
beq Pass8
|
||||
Fail8:
|
||||
PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail8
|
||||
Pass8:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckD
|
||||
bne Fail8
|
||||
PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
WaitNMI() // Wait For VSync
|
||||
|
||||
ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word
|
||||
|
||||
WaitNMI() // Wait For VSync
|
||||
|
||||
// Print Syntax/Opcode Text
|
||||
PrintText(ASLDP, $F902, 26) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
clv // Clear Overflow Flag
|
||||
|
||||
// Run Test
|
||||
lda.b #$80 // A = $80
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
asl.b AbsoluteData // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA12, 1) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
lda.b AbsoluteData // A = Result Data
|
||||
cmp.w ASLResultCheckA
|
||||
beq Pass9
|
||||
Fail9:
|
||||
PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail9
|
||||
Pass9:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckA
|
||||
bne Fail9
|
||||
PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.b #$7F // A = $7F
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
asl.b AbsoluteData // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA52, 1) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
lda.b AbsoluteData // A = Result Data
|
||||
cmp.w ASLResultCheckB
|
||||
beq Pass10
|
||||
Fail10:
|
||||
PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail10
|
||||
Pass10:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckB
|
||||
bne Fail10
|
||||
PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.w #$8000 // A = $8000
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
asl.b AbsoluteData // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA92, 2) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
ldx.b AbsoluteData // X = Result Data
|
||||
cpx.w ASLResultCheckC
|
||||
beq Pass11
|
||||
Fail11:
|
||||
PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail11
|
||||
Pass11:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckC
|
||||
bne Fail11
|
||||
PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.w #$7FFF // A = $7FFF
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
asl.b AbsoluteData // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
ldx.b AbsoluteData // X = Result Data
|
||||
cpx.w ASLResultCheckD
|
||||
beq Pass12
|
||||
Fail12:
|
||||
PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail12
|
||||
Pass12:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckD
|
||||
bne Fail12
|
||||
PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
WaitNMI() // Wait For VSync
|
||||
|
||||
ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word
|
||||
|
||||
WaitNMI() // Wait For VSync
|
||||
|
||||
// Print Syntax/Opcode Text
|
||||
PrintText(ASLAddrX, $F902, 26) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
clv // Clear Overflow Flag
|
||||
|
||||
// Run Test
|
||||
lda.b #$80 // A = $80
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
ldx.w #0 // X = 0
|
||||
asl.w AbsoluteData,x // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA12, 1) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
lda.b AbsoluteData // A = Result Data
|
||||
cmp.w ASLResultCheckA
|
||||
beq Pass13
|
||||
Fail13:
|
||||
PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail13
|
||||
Pass13:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckA
|
||||
bne Fail13
|
||||
PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.b #$7F // A = $7F
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
ldx.w #0 // X = 0
|
||||
asl.w AbsoluteData,x // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA52, 1) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
lda.b AbsoluteData // A = Result Data
|
||||
cmp.w ASLResultCheckB
|
||||
beq Pass14
|
||||
Fail14:
|
||||
PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail14
|
||||
Pass14:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckB
|
||||
bne Fail14
|
||||
PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.w #$8000 // A = $8000
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
ldx.w #0 // X = 0
|
||||
asl.w AbsoluteData,x // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA92, 2) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
ldx.b AbsoluteData // X = Result Data
|
||||
cpx.w ASLResultCheckC
|
||||
beq Pass15
|
||||
Fail15:
|
||||
PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail15
|
||||
Pass15:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckC
|
||||
bne Fail15
|
||||
PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.w #$7FFF // A = $7FFF
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
ldx.w #0 // X = 0
|
||||
asl.w AbsoluteData,x // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
ldx.b AbsoluteData // X = Result Data
|
||||
cpx.w ASLResultCheckD
|
||||
beq Pass16
|
||||
Fail16:
|
||||
PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail16
|
||||
Pass16:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckD
|
||||
bne Fail16
|
||||
PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
WaitNMI() // Wait For VSync
|
||||
|
||||
ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word
|
||||
|
||||
WaitNMI() // Wait For VSync
|
||||
|
||||
// Print Syntax/Opcode Text
|
||||
PrintText(ASLDPX, $F902, 26) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
clv // Clear Overflow Flag
|
||||
|
||||
// Run Test
|
||||
lda.b #$80 // A = $80
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
ldx.w #0 // X = 0
|
||||
asl.b AbsoluteData,x // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA12, 1) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
lda.b AbsoluteData // A = Result Data
|
||||
cmp.w ASLResultCheckA
|
||||
beq Pass17
|
||||
Fail17:
|
||||
PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail17
|
||||
Pass17:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckA
|
||||
bne Fail17
|
||||
PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.b #$7F // A = $7F
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
ldx.w #0 // X = 0
|
||||
asl.b AbsoluteData,x // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA52, 1) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
lda.b AbsoluteData // A = Result Data
|
||||
cmp.w ASLResultCheckB
|
||||
beq Pass18
|
||||
Fail18:
|
||||
PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail18
|
||||
Pass18:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckB
|
||||
bne Fail18
|
||||
PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.w #$8000 // A = $8000
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
ldx.w #0 // X = 0
|
||||
asl.b AbsoluteData,x // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FA92, 2) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
ldx.b AbsoluteData // X = Result Data
|
||||
cpx.w ASLResultCheckC
|
||||
beq Pass19
|
||||
Fail19:
|
||||
PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail19
|
||||
Pass19:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckC
|
||||
bne Fail19
|
||||
PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Modes Text
|
||||
PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$08 // Reset Decimal Flag
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Run Test
|
||||
lda.w #$7FFF // A = $7FFF
|
||||
sta.b AbsoluteData // Store Absolute Data
|
||||
ldx.w #0 // X = 0
|
||||
asl.b AbsoluteData,x // Memory <<= 1
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Result & Processor Status Flag Data
|
||||
PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data
|
||||
PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data
|
||||
|
||||
// Check Result & Processor Status Flag Data
|
||||
ldx.b AbsoluteData // X = Result Data
|
||||
cpx.w ASLResultCheckD
|
||||
beq Pass20
|
||||
Fail20:
|
||||
PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail20
|
||||
Pass20:
|
||||
lda.b PSRFlagData // A = Processor Status Flag Data
|
||||
cmp.w PSRResultCheckD
|
||||
bne Fail20
|
||||
PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
Loop:
|
||||
jmp Loop
|
||||
|
||||
Title:
|
||||
db "CPU Test ASL (Shift Left):"
|
||||
|
||||
PageBreak:
|
||||
db "------------------------------"
|
||||
|
||||
Key:
|
||||
db "Modes | Result | NVZC | Test |"
|
||||
Binary8Bit:
|
||||
db "BIN,8"
|
||||
Binary16Bit:
|
||||
db "BIN,16"
|
||||
Fail:
|
||||
db "FAIL"
|
||||
Pass:
|
||||
db "PASS"
|
||||
|
||||
ASLA:
|
||||
db "ASL A (Opcode: $0A)"
|
||||
ASLAddr:
|
||||
db "ASL addr (Opcode: $0E)"
|
||||
ASLDP:
|
||||
db "ASL dp (Opcode: $06)"
|
||||
ASLAddrX:
|
||||
db "ASL addr,X (Opcode: $1E)"
|
||||
ASLDPX:
|
||||
db "ASL dp,X (Opcode: $16)"
|
||||
|
||||
ASLResultCheckA:
|
||||
db $00
|
||||
PSRResultCheckA:
|
||||
db $27
|
||||
|
||||
ASLResultCheckB:
|
||||
db $FE
|
||||
PSRResultCheckB:
|
||||
db $A4
|
||||
|
||||
ASLResultCheckC:
|
||||
dw $0000
|
||||
PSRResultCheckC:
|
||||
db $07
|
||||
|
||||
ASLResultCheckD:
|
||||
dw $FFFE
|
||||
PSRResultCheckD:
|
||||
db $84
|
||||
|
||||
BGCHR:
|
||||
include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes)
|
||||
BGPAL:
|
||||
dw $7800, $7FFF // Blue / White Palette (4 Bytes)
|
||||
BGCLEAR:
|
||||
dw $0020 // BG Clear Character Space " " Fixed Word
|
||||
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/CPUASL.png
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/CPUASL.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.0 KiB |
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/CPUASL.sfc
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/CPUASL.sfc
Normal file
Binary file not shown.
957
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/Font8x8.asm
Normal file
957
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/Font8x8.asm
Normal file
@ -0,0 +1,957 @@
|
||||
fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes
|
||||
|
||||
// $20: Space " "
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $21: Exclamation mark "!"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $22: Quotation mark """
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $23: Cross hatch "#"
|
||||
db %00010100
|
||||
db %00010100
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $24: Dollar sign "$"
|
||||
db %00111100
|
||||
db %01101010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01010110
|
||||
db %00111100
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $25: Percent sign "%"
|
||||
db %00100010
|
||||
db %01010100
|
||||
db %00101000
|
||||
db %00010100
|
||||
db %00101010
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $26: Ampersand "&"
|
||||
db %00110000
|
||||
db %01001000
|
||||
db %00110010
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00110010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $27: Closing single quote "'"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $28: Opening parentheses "("
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
|
||||
// $29: Closing parentheses ")"
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
|
||||
// $2A: Asterisk "*"
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2B: Plus "+"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2C: Comma ","
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $2D: Hyphen "-"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2E: Period "."
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2F: Forward slash "/"
|
||||
db %00000010
|
||||
db %00000110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01100000
|
||||
db %01000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $30: 0
|
||||
db %00111010
|
||||
db %01100100
|
||||
db %01001010
|
||||
db %01010010
|
||||
db %00100110
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $31: 1
|
||||
db %00011000
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $32: 2
|
||||
db %00111000
|
||||
db %01001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $33: 3
|
||||
db %00111100
|
||||
db %01000110
|
||||
db %00011100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $34: 4
|
||||
db %00001100
|
||||
db %00011100
|
||||
db %00101100
|
||||
db %01001100
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $35: 5
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $36: 6
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $37: 7
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $38: 8
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $39: 9
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %00000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $3A: Colon ":"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3B: Semicolon ";"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $3C: Less than sign "<"
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3D: Equals sign "="
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3E: Greater than sign ">"
|
||||
db %00000000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3F: Question mark "?"
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
|
||||
// $40: At sign "@"
|
||||
db %01111100
|
||||
db %10000010
|
||||
db %10111010
|
||||
db %10101010
|
||||
db %10111110
|
||||
db %01000000
|
||||
db %00111110
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $41: A
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00100100
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $42: B
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $43: C
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $44: D
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $45: E
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $46: F
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $47: G
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $48: H
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $49: I
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4A: J
|
||||
db %00111110
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %01001100
|
||||
db %01111100
|
||||
db %00111000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4B: K
|
||||
db %01100110
|
||||
db %01101100
|
||||
db %01111000
|
||||
db %01111000
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4C: L
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4D: M
|
||||
db %01000010
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4E: N
|
||||
db %01000110
|
||||
db %01100110
|
||||
db %01110110
|
||||
db %01111110
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4F: O
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $50: P
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $51: Q
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100010
|
||||
db %01101010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $52: R
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $53: S
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $54: T
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $55: U
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $56: V
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00100100
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $57: W
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $58: X
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $59: Y
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5A: Z
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $5B: Opening square bracket "["
|
||||
db %00011100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011100
|
||||
|
||||
// $5C: Back slash "\"
|
||||
db %01000000
|
||||
db %01100000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00000110
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $5D: Closing square bracket "]"
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111000
|
||||
|
||||
// $5E: Caret "^"
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5F: Underscore "_"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %11111111
|
||||
|
||||
// $60: Opening single quote "`"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $61: a
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01100100
|
||||
db %01100100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $62: b
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00111100
|
||||
db %00110010
|
||||
db %00110010
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $63: c
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $64: d
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $65: e
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01101000
|
||||
db %01110010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $66: f
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011100
|
||||
db %00110010
|
||||
db %00110000
|
||||
db %01111100
|
||||
db %00110000
|
||||
db %00110000
|
||||
|
||||
// $67: g
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111010
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $68: h
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $69: i
|
||||
db %00110000
|
||||
db %00000000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6A: j
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $6B: k
|
||||
db %01100000
|
||||
db %01100100
|
||||
db %01101000
|
||||
db %01111000
|
||||
db %01100100
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6C: l
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6D: m
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01010100
|
||||
db %01101010
|
||||
db %01101010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6E: n
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6F: o
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $70: p
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
|
||||
// $71: q
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00110100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111100
|
||||
db %00001110
|
||||
db %00001100
|
||||
|
||||
// $72: r
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $73: s
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %00011000
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $74: t
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %01111000
|
||||
db %00110000
|
||||
db %00110010
|
||||
db %00011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $75: u
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $76: v
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $77: w
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %00101100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $78: x
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $79: y
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $7A: z
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $7B: Opening curly bracket "{"
|
||||
db %00011100
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011100
|
||||
|
||||
// $7C: Vertical line "|"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
|
||||
// $7D: Closing curly bracket "{"
|
||||
db %00111000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111000
|
||||
|
||||
// $7E: Tilde "~"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01110000
|
||||
db %01011010
|
||||
db %00001110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
507
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/LIB/SNES.INC
Normal file
507
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/LIB/SNES.INC
Normal file
@ -0,0 +1,507 @@
|
||||
//============== (Key: R=Read, W=Write, D=Double Read/Write)
|
||||
// SNES Include
|
||||
//==============
|
||||
// Memory Map
|
||||
constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW
|
||||
|
||||
// PPU Picture Processing Unit Ports (Write-Only)
|
||||
constant REG_INIDISP($2100) // Display Control 1 1B/W
|
||||
constant REG_OBSEL($2101) // Object Size & Object Base 1B/W
|
||||
constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W
|
||||
constant REG_OAMDATA($2104) // OAM Data Write 1B/W D
|
||||
constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W
|
||||
constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W
|
||||
constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W
|
||||
constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W
|
||||
constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D
|
||||
constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D
|
||||
constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W
|
||||
constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W
|
||||
constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W
|
||||
constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W
|
||||
constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W
|
||||
constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D
|
||||
constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D
|
||||
constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D
|
||||
constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D
|
||||
constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D
|
||||
constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D
|
||||
constant REG_CGADD($2121) // Palette CGRAM Address 1B/W
|
||||
constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D
|
||||
constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W
|
||||
constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W
|
||||
constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W
|
||||
constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W
|
||||
constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W
|
||||
constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W
|
||||
constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W
|
||||
constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W
|
||||
constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W
|
||||
constant REG_TM($212C) // Main Screen Designation 1B/W
|
||||
constant REG_TS($212D) // Sub Screen Designation 1B/W
|
||||
constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W
|
||||
constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W
|
||||
constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W
|
||||
constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W
|
||||
constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W
|
||||
constant REG_SETINI($2133) // Display Control 2 1B/W
|
||||
|
||||
// PPU Picture Processing Unit Ports (Read-Only)
|
||||
constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R
|
||||
constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R
|
||||
constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R
|
||||
constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R
|
||||
constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D
|
||||
constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R
|
||||
constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R
|
||||
constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D
|
||||
constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D
|
||||
constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D
|
||||
constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R
|
||||
constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R
|
||||
|
||||
// APU Audio Processing Unit Ports (Read/Write)
|
||||
constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW
|
||||
constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW
|
||||
constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW
|
||||
constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW
|
||||
// $2140..$2143 - APU Ports Mirrored To $2144..$217F
|
||||
|
||||
// WRAM Access Ports
|
||||
constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW
|
||||
constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W
|
||||
constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W
|
||||
constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W
|
||||
// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus)
|
||||
// $2200..$3FFF - Unused Region (A-Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz)
|
||||
// ($4000..$4015 - Unused Region (Open Bus)
|
||||
constant REG_JOYWR($4016) // Joypad Output 1B/W
|
||||
constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R
|
||||
constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R
|
||||
// $4018..$41FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Write-only, Read=Open Bus)
|
||||
constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W
|
||||
constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W
|
||||
constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W
|
||||
constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W
|
||||
constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W
|
||||
constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W
|
||||
constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W
|
||||
constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W
|
||||
constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W
|
||||
constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W
|
||||
constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W
|
||||
constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W
|
||||
// $420E..$420F - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Read-only)
|
||||
constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R
|
||||
constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R
|
||||
constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R
|
||||
constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R
|
||||
constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R
|
||||
constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R
|
||||
constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R
|
||||
constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R
|
||||
// $4220..$42FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port)
|
||||
constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW
|
||||
// $430C..$430E - Unused Region (Open Bus)
|
||||
constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW
|
||||
|
||||
constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW
|
||||
// $431C..$431E - Unused Region (Open Bus)
|
||||
constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW
|
||||
|
||||
constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW
|
||||
// $432C..$432E - Unused Region (Open Bus)
|
||||
constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW
|
||||
|
||||
constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW
|
||||
// $433C..$433E - Unused Region (Open Bus)
|
||||
constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW
|
||||
|
||||
constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW
|
||||
// $434C..$434E - Unused Region (Open Bus)
|
||||
constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW
|
||||
|
||||
constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW
|
||||
// $435C..$435E - Unused Region (Open Bus)
|
||||
constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW
|
||||
|
||||
constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW
|
||||
// $436C..$436E - Unused Region (Open Bus)
|
||||
constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW
|
||||
|
||||
constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW
|
||||
// $437C..$437E - Unused Region (Open Bus)
|
||||
constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW
|
||||
// $4380..$5FFF - Unused Region (Open Bus)
|
||||
|
||||
// Further Memory
|
||||
// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges)
|
||||
// $8000..$FFFF - Cartridge ROM
|
||||
|
||||
//================================================
|
||||
// ReadD16 - Read Double 8-bit To Memory (16-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro ReadD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} // Load Source High Byte
|
||||
sta {DEST} + 1 // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// ReadD16Index - Read Double 8-bit To Index (16-Bit)
|
||||
//====================================================
|
||||
// SRC: Source Address
|
||||
// REG: Destination Index Register (x, y)
|
||||
macro ReadD16Index(SRC, REG) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
lda {SRC} // Load Source High Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
ta{REG} // Transfer 16-Bit A To 16-Bit REG
|
||||
}
|
||||
|
||||
//================================================
|
||||
// WriteD8 - Write Memory To Double 8-bit (8-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD8(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//==================================================
|
||||
// WriteD16 - Write Memory To Double 8-bit (16-Bit)
|
||||
//==================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} + 1 // Load Source High Byte
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// WriteD8Index - Write Index To Double 8-bit (8-Bit)
|
||||
//====================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD8Index(REG, DEST) {
|
||||
t{REG}a // Transfer 8-Bit REG To 8-Bit A
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//======================================================
|
||||
// WriteD16Index - Write Index To Double 8-bit (16-Bit)
|
||||
//======================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD16Index(REG, DEST) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Transfer 16-Bit REG To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//=====================
|
||||
// SNES Initialisation
|
||||
//=====================
|
||||
// ROMSPEED: ROM Speed (SLOWROM, FASTROM)
|
||||
constant SLOWROM(0) // Access Cycle Designation (Slow ROM)
|
||||
constant FASTROM(1) // Access Cycle Designation (Fast ROM)
|
||||
macro SNES_INIT(ROMSPEED) {
|
||||
sei // Disable Interrupts
|
||||
clc // Clear Carry To Switch To Native Mode
|
||||
xce // Xchange Carry & Emulation Bit (Native Mode)
|
||||
|
||||
phk
|
||||
plb
|
||||
rep #$38
|
||||
|
||||
ldx.w #$1FFF // Set Stack To $1FFF
|
||||
txs // Transfer Index Register X To Stack Pointer
|
||||
|
||||
lda.w #$0000
|
||||
tcd
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
|
||||
lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1
|
||||
sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM)
|
||||
|
||||
lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness)
|
||||
sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100)
|
||||
|
||||
stz.w REG_OBSEL // Object Size & Object Base ($2101)
|
||||
stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102)
|
||||
stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103)
|
||||
stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105)
|
||||
stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106)
|
||||
stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107)
|
||||
stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108)
|
||||
stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109)
|
||||
stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A)
|
||||
stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B)
|
||||
stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114)
|
||||
|
||||
lda.b #$01
|
||||
stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B)
|
||||
sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D)
|
||||
stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E)
|
||||
sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120)
|
||||
|
||||
stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123)
|
||||
stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124)
|
||||
stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125)
|
||||
stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126)
|
||||
stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127)
|
||||
stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128)
|
||||
stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129)
|
||||
stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A)
|
||||
stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B)
|
||||
stz.w REG_TM // Main Screen Designation = 0 ($212C)
|
||||
stz.w REG_TS // Sub Screen Designation = 0 ($212D)
|
||||
stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E)
|
||||
stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F)
|
||||
|
||||
lda.b #$30
|
||||
sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130)
|
||||
stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131)
|
||||
|
||||
lda.b #$E0
|
||||
sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132)
|
||||
stz.w REG_SETINI // Display Control 2 = 0 ($2133)
|
||||
|
||||
stz.w REG_JOYWR // Joypad Output = 0 ($4016)
|
||||
|
||||
stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200)
|
||||
|
||||
lda.b #$FF
|
||||
sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201)
|
||||
|
||||
stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202)
|
||||
stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203)
|
||||
stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204)
|
||||
stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205)
|
||||
stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206)
|
||||
stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207)
|
||||
stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208)
|
||||
stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209)
|
||||
stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A)
|
||||
stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B)
|
||||
stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C)
|
||||
|
||||
// Clear OAM
|
||||
ldx.w #$0080
|
||||
lda.b #$E0
|
||||
-
|
||||
sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104)
|
||||
sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
ldx.w #$0020
|
||||
-
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
// Clear WRAM
|
||||
ldy.w #$0000
|
||||
sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181)
|
||||
stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183)
|
||||
|
||||
ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom
|
||||
lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank)
|
||||
stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302)
|
||||
sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
nop // Delay
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B)
|
||||
|
||||
// VRAM
|
||||
lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119)
|
||||
sta.w REG_VMAIN // VRAM Address Increment Mode ($2115)
|
||||
ldy.w #$0000
|
||||
sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
// CGRAM
|
||||
stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121)
|
||||
ldx.w #$200 // 512 Byte
|
||||
stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305)
|
||||
ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
jml +
|
||||
|
||||
CONST_ZERO:
|
||||
dw $0000
|
||||
|
||||
+
|
||||
}
|
||||
558
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/LIB/SNES_GFX.INC
Normal file
558
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/LIB/SNES_GFX.INC
Normal file
@ -0,0 +1,558 @@
|
||||
//===============
|
||||
// SNES Graphics
|
||||
//===============
|
||||
|
||||
//=============================
|
||||
// WaitNMI - Wait For NMI Flag
|
||||
//=============================
|
||||
macro WaitNMI() {
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
}
|
||||
|
||||
//======================================
|
||||
// WaitHV - Wait For H/V Timer IRQ Flag
|
||||
//======================================
|
||||
macro WaitHV() {
|
||||
-
|
||||
bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag
|
||||
bpl - // Wait For H/V Timer IRQ Flag
|
||||
}
|
||||
|
||||
//========================================
|
||||
// WaitHVB - Wait For V-Blank Period Flag
|
||||
//========================================
|
||||
macro WaitHVB() {
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
}
|
||||
|
||||
//================================================================
|
||||
// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing)
|
||||
//================================================================
|
||||
macro FadeIN() {
|
||||
ldx.w #$0000 // Set X To Mininmum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
inx // Increments Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$0F // Compare With Maximum Brightness Level (15)
|
||||
bne - // IF (Screen != Maximum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//=================================================================
|
||||
// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing)
|
||||
//=================================================================
|
||||
macro FadeOUT() {
|
||||
ldx.w #$000F // Set X To Maximum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
dex // Decrement Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$00 // Compare With Minimum Brightness Level
|
||||
bne - // IF (Screen != Minimum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//======================================
|
||||
// LoadPAL - Load Palette Data To CGRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadPAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==========================================
|
||||
// UpdatePAL - Update Palette Data To CGRAM
|
||||
//==========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdatePAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearLOVRAM - Clear VRAM Lo Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearHIVRAM - Clear VRAM Hi Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===================================
|
||||
// ClearVRAM - Clear VRAM Fixed Word
|
||||
//===================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
// Transfer Lo Byte
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Transfer Hi Byte
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==================================
|
||||
// LoadVRAM - Load GFX Data To VRAM
|
||||
//==================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================================
|
||||
// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride
|
||||
//========================================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// STRIDE: Dest Offset Stride
|
||||
// COUNT: Number Of DMA Transfers
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
-
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
txa // A = X
|
||||
clc // Clear Carry Flag
|
||||
adc.w #{STRIDE} >> 1
|
||||
tax // X = A
|
||||
lda.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1
|
||||
bne -
|
||||
}
|
||||
|
||||
//======================================
|
||||
// UpdateVRAM - Update GFX Data To VRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdateVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===========================================
|
||||
// LoadM7VRAM - Load Mode 7 GFX Data To VRAM
|
||||
//===========================================
|
||||
// SRCMAP: 24-Bit Address Of Source Map Data
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZEMAP: Size Of Map Data (BYTE Size)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) {
|
||||
// Load Mode7 Map Data To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCMAP} // Set Source Offset (Map)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCMAP} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map)
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset (Tiles)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8 - Scroll GFX BG From Memory (8-Bit)
|
||||
//===============================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8(BGSCR, BGPOS, DIR) {
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16 - Scroll GFX BG From Memory (16-Bit)
|
||||
//=================================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16(BGSCR, BGPOS, DIR) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
lda {BGSCR} + 1 // Load BG Scroll Position High Byte
|
||||
sta {BGPOS} // Store BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8I - Scroll GFX BG From Index (8-Bit)
|
||||
//===============================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
t{REG}a // Swaps 8-Bit Index To 8-Bit A
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16I - Scroll GFX BG From Index (16-Bit)
|
||||
//=================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Word
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Swaps 16-Bit Index To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {BGPOS} // Store A To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//======================================
|
||||
// Mode7CALC - Mode7 Matrix Calculation
|
||||
//======================================
|
||||
// A: Mode7 COS A Word
|
||||
// B: Mode7 SIN A Word
|
||||
// C: Mode7 SIN B Word
|
||||
// D: Mode7 COS B Word
|
||||
// ANGLE: Mode7 Angle Byte
|
||||
// SX: Mode7 Scale X Word
|
||||
// SY: Mode7 Scale Y Word
|
||||
// SINCOS: Mode7 SINCOS Table
|
||||
macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) {
|
||||
lda.b {ANGLE} // Load Angle To A
|
||||
tax // Transfer A To X
|
||||
|
||||
// Calculate B & C (SIN)
|
||||
// B
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {B}
|
||||
// C
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1 // High Byte
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
eor.b #$FF // Make Negative
|
||||
inc
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {C}
|
||||
|
||||
// Change X Index To Point To COS Values (X + 64)
|
||||
txa // Transfer X Index To A
|
||||
clc // Clear Carry Flag
|
||||
adc.b #64 // Add 64 With Carry
|
||||
tax // Transfer A To X Index
|
||||
|
||||
// Calculate A & D (COS)
|
||||
// A
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {A}
|
||||
// D
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {D}
|
||||
|
||||
// Store Result To Matrix
|
||||
lda.b {A}
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {A} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
|
||||
lda.b {B}
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
lda.b {B} + 1
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
|
||||
lda.b {C}
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
lda.b {C} + 1
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
|
||||
lda.b {D}
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
lda.b {D} + 1
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
//=============
|
||||
// SNES Header
|
||||
//=============
|
||||
seek($FFC0)
|
||||
// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes)
|
||||
db "65816 CPU TEST ASL "
|
||||
// "123456789012345678901"
|
||||
|
||||
// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode)
|
||||
db $20
|
||||
// ||___________________Map Mode:
|
||||
// | $X0 = LoROM/32K Banks (Mode 20)
|
||||
// | $X1 = HiROM/64K Banks (Mode 21)
|
||||
// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable)
|
||||
// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable)
|
||||
// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM)
|
||||
// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable)
|
||||
|
||||
// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type)
|
||||
db $00
|
||||
// ||___________________Type:
|
||||
// | $00 = ROM
|
||||
// | $01 = ROM+RAM
|
||||
// Co-processor: $02 = ROM+RAM+Battery
|
||||
// $0X = DSP $X3 = ROM+Co-processor
|
||||
// $1X = GSU $X4 = ROM+Co-processor+RAM
|
||||
// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery
|
||||
// $3X = SA-1 $X6 = ROM+Co-processor+Battery
|
||||
// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513
|
||||
// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked
|
||||
|
||||
// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits)
|
||||
db $01
|
||||
// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit)
|
||||
// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit)
|
||||
// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit)
|
||||
// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit)
|
||||
// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit)
|
||||
// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit)
|
||||
|
||||
// RAM SIZE
|
||||
db $00
|
||||
// $00 = None, $04 = 16Kb
|
||||
// $01 = 2Kb, $05 = 32Kb
|
||||
// $02 = 4Kb, $06 = 64Kb
|
||||
// $03 = 8Kb, $07 = 128Kb
|
||||
|
||||
// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz)
|
||||
db $00
|
||||
// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL)
|
||||
// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL)
|
||||
// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL)
|
||||
// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL)
|
||||
// $04 = Finland (PAL), $0D = South (K)orea (NTSC)
|
||||
// $05 = Denmark (PAL), $0E = (A)Common (ANY)
|
||||
// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC)
|
||||
// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M)
|
||||
// $08 = (S)pain (PAL), $11 = (U)Australia (PAL)
|
||||
|
||||
// DEVELOPER ID CODE
|
||||
db $00
|
||||
// $00 = None
|
||||
// $01 = Nintendo
|
||||
// $33 = New (Uses Extended Header)
|
||||
|
||||
// ROM VERSION NUMBER
|
||||
db $00
|
||||
// $00 = 1.00, $01 = 1.01
|
||||
|
||||
// COMPLEMENT CHECK
|
||||
db "CC"
|
||||
// CHECKSUM
|
||||
db "CS"
|
||||
|
||||
// NATIVE VECTOR (65C816 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (BRK Opcode)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $0000 // RESET VECTOR (Unused)
|
||||
dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt)
|
||||
|
||||
// EMU VECTOR (6502 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (Unused)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET)
|
||||
dw $0000 // IRQ/BRK VECTOR
|
||||
1
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/make.bat
Normal file
1
OSBindings/Mac/Clock SignalTests/krom 65816/ASL/make.bat
Normal file
@ -0,0 +1 @@
|
||||
bass CPUASL.asm
|
||||
1728
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/CPUBIT.asm
Normal file
1728
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/CPUBIT.asm
Normal file
File diff suppressed because it is too large
Load Diff
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/CPUBIT.png
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/CPUBIT.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 1.9 KiB |
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/CPUBIT.sfc
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/CPUBIT.sfc
Normal file
Binary file not shown.
957
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/Font8x8.asm
Normal file
957
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/Font8x8.asm
Normal file
@ -0,0 +1,957 @@
|
||||
fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes
|
||||
|
||||
// $20: Space " "
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $21: Exclamation mark "!"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $22: Quotation mark """
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $23: Cross hatch "#"
|
||||
db %00010100
|
||||
db %00010100
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $24: Dollar sign "$"
|
||||
db %00111100
|
||||
db %01101010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01010110
|
||||
db %00111100
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $25: Percent sign "%"
|
||||
db %00100010
|
||||
db %01010100
|
||||
db %00101000
|
||||
db %00010100
|
||||
db %00101010
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $26: Ampersand "&"
|
||||
db %00110000
|
||||
db %01001000
|
||||
db %00110010
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00110010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $27: Closing single quote "'"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $28: Opening parentheses "("
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
|
||||
// $29: Closing parentheses ")"
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
|
||||
// $2A: Asterisk "*"
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2B: Plus "+"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2C: Comma ","
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $2D: Hyphen "-"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2E: Period "."
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2F: Forward slash "/"
|
||||
db %00000010
|
||||
db %00000110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01100000
|
||||
db %01000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $30: 0
|
||||
db %00111010
|
||||
db %01100100
|
||||
db %01001010
|
||||
db %01010010
|
||||
db %00100110
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $31: 1
|
||||
db %00011000
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $32: 2
|
||||
db %00111000
|
||||
db %01001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $33: 3
|
||||
db %00111100
|
||||
db %01000110
|
||||
db %00011100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $34: 4
|
||||
db %00001100
|
||||
db %00011100
|
||||
db %00101100
|
||||
db %01001100
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $35: 5
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $36: 6
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $37: 7
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $38: 8
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $39: 9
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %00000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $3A: Colon ":"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3B: Semicolon ";"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $3C: Less than sign "<"
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3D: Equals sign "="
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3E: Greater than sign ">"
|
||||
db %00000000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3F: Question mark "?"
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
|
||||
// $40: At sign "@"
|
||||
db %01111100
|
||||
db %10000010
|
||||
db %10111010
|
||||
db %10101010
|
||||
db %10111110
|
||||
db %01000000
|
||||
db %00111110
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $41: A
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00100100
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $42: B
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $43: C
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $44: D
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $45: E
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $46: F
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $47: G
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $48: H
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $49: I
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4A: J
|
||||
db %00111110
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %01001100
|
||||
db %01111100
|
||||
db %00111000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4B: K
|
||||
db %01100110
|
||||
db %01101100
|
||||
db %01111000
|
||||
db %01111000
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4C: L
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4D: M
|
||||
db %01000010
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4E: N
|
||||
db %01000110
|
||||
db %01100110
|
||||
db %01110110
|
||||
db %01111110
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4F: O
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $50: P
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $51: Q
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100010
|
||||
db %01101010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $52: R
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $53: S
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $54: T
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $55: U
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $56: V
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00100100
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $57: W
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $58: X
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $59: Y
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5A: Z
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $5B: Opening square bracket "["
|
||||
db %00011100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011100
|
||||
|
||||
// $5C: Back slash "\"
|
||||
db %01000000
|
||||
db %01100000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00000110
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $5D: Closing square bracket "]"
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111000
|
||||
|
||||
// $5E: Caret "^"
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5F: Underscore "_"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %11111111
|
||||
|
||||
// $60: Opening single quote "`"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $61: a
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01100100
|
||||
db %01100100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $62: b
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00111100
|
||||
db %00110010
|
||||
db %00110010
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $63: c
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $64: d
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $65: e
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01101000
|
||||
db %01110010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $66: f
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011100
|
||||
db %00110010
|
||||
db %00110000
|
||||
db %01111100
|
||||
db %00110000
|
||||
db %00110000
|
||||
|
||||
// $67: g
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111010
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $68: h
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $69: i
|
||||
db %00110000
|
||||
db %00000000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6A: j
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $6B: k
|
||||
db %01100000
|
||||
db %01100100
|
||||
db %01101000
|
||||
db %01111000
|
||||
db %01100100
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6C: l
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6D: m
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01010100
|
||||
db %01101010
|
||||
db %01101010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6E: n
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6F: o
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $70: p
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
|
||||
// $71: q
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00110100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111100
|
||||
db %00001110
|
||||
db %00001100
|
||||
|
||||
// $72: r
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $73: s
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %00011000
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $74: t
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %01111000
|
||||
db %00110000
|
||||
db %00110010
|
||||
db %00011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $75: u
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $76: v
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $77: w
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %00101100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $78: x
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $79: y
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $7A: z
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $7B: Opening curly bracket "{"
|
||||
db %00011100
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011100
|
||||
|
||||
// $7C: Vertical line "|"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
|
||||
// $7D: Closing curly bracket "{"
|
||||
db %00111000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111000
|
||||
|
||||
// $7E: Tilde "~"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01110000
|
||||
db %01011010
|
||||
db %00001110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
507
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/LIB/SNES.INC
Normal file
507
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/LIB/SNES.INC
Normal file
@ -0,0 +1,507 @@
|
||||
//============== (Key: R=Read, W=Write, D=Double Read/Write)
|
||||
// SNES Include
|
||||
//==============
|
||||
// Memory Map
|
||||
constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW
|
||||
|
||||
// PPU Picture Processing Unit Ports (Write-Only)
|
||||
constant REG_INIDISP($2100) // Display Control 1 1B/W
|
||||
constant REG_OBSEL($2101) // Object Size & Object Base 1B/W
|
||||
constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W
|
||||
constant REG_OAMDATA($2104) // OAM Data Write 1B/W D
|
||||
constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W
|
||||
constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W
|
||||
constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W
|
||||
constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W
|
||||
constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D
|
||||
constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D
|
||||
constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W
|
||||
constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W
|
||||
constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W
|
||||
constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W
|
||||
constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W
|
||||
constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D
|
||||
constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D
|
||||
constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D
|
||||
constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D
|
||||
constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D
|
||||
constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D
|
||||
constant REG_CGADD($2121) // Palette CGRAM Address 1B/W
|
||||
constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D
|
||||
constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W
|
||||
constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W
|
||||
constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W
|
||||
constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W
|
||||
constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W
|
||||
constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W
|
||||
constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W
|
||||
constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W
|
||||
constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W
|
||||
constant REG_TM($212C) // Main Screen Designation 1B/W
|
||||
constant REG_TS($212D) // Sub Screen Designation 1B/W
|
||||
constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W
|
||||
constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W
|
||||
constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W
|
||||
constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W
|
||||
constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W
|
||||
constant REG_SETINI($2133) // Display Control 2 1B/W
|
||||
|
||||
// PPU Picture Processing Unit Ports (Read-Only)
|
||||
constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R
|
||||
constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R
|
||||
constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R
|
||||
constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R
|
||||
constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D
|
||||
constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R
|
||||
constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R
|
||||
constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D
|
||||
constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D
|
||||
constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D
|
||||
constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R
|
||||
constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R
|
||||
|
||||
// APU Audio Processing Unit Ports (Read/Write)
|
||||
constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW
|
||||
constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW
|
||||
constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW
|
||||
constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW
|
||||
// $2140..$2143 - APU Ports Mirrored To $2144..$217F
|
||||
|
||||
// WRAM Access Ports
|
||||
constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW
|
||||
constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W
|
||||
constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W
|
||||
constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W
|
||||
// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus)
|
||||
// $2200..$3FFF - Unused Region (A-Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz)
|
||||
// ($4000..$4015 - Unused Region (Open Bus)
|
||||
constant REG_JOYWR($4016) // Joypad Output 1B/W
|
||||
constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R
|
||||
constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R
|
||||
// $4018..$41FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Write-only, Read=Open Bus)
|
||||
constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W
|
||||
constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W
|
||||
constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W
|
||||
constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W
|
||||
constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W
|
||||
constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W
|
||||
constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W
|
||||
constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W
|
||||
constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W
|
||||
constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W
|
||||
constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W
|
||||
constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W
|
||||
// $420E..$420F - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Read-only)
|
||||
constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R
|
||||
constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R
|
||||
constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R
|
||||
constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R
|
||||
constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R
|
||||
constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R
|
||||
constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R
|
||||
constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R
|
||||
// $4220..$42FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port)
|
||||
constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW
|
||||
// $430C..$430E - Unused Region (Open Bus)
|
||||
constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW
|
||||
|
||||
constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW
|
||||
// $431C..$431E - Unused Region (Open Bus)
|
||||
constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW
|
||||
|
||||
constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW
|
||||
// $432C..$432E - Unused Region (Open Bus)
|
||||
constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW
|
||||
|
||||
constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW
|
||||
// $433C..$433E - Unused Region (Open Bus)
|
||||
constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW
|
||||
|
||||
constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW
|
||||
// $434C..$434E - Unused Region (Open Bus)
|
||||
constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW
|
||||
|
||||
constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW
|
||||
// $435C..$435E - Unused Region (Open Bus)
|
||||
constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW
|
||||
|
||||
constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW
|
||||
// $436C..$436E - Unused Region (Open Bus)
|
||||
constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW
|
||||
|
||||
constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW
|
||||
// $437C..$437E - Unused Region (Open Bus)
|
||||
constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW
|
||||
// $4380..$5FFF - Unused Region (Open Bus)
|
||||
|
||||
// Further Memory
|
||||
// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges)
|
||||
// $8000..$FFFF - Cartridge ROM
|
||||
|
||||
//================================================
|
||||
// ReadD16 - Read Double 8-bit To Memory (16-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro ReadD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} // Load Source High Byte
|
||||
sta {DEST} + 1 // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// ReadD16Index - Read Double 8-bit To Index (16-Bit)
|
||||
//====================================================
|
||||
// SRC: Source Address
|
||||
// REG: Destination Index Register (x, y)
|
||||
macro ReadD16Index(SRC, REG) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
lda {SRC} // Load Source High Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
ta{REG} // Transfer 16-Bit A To 16-Bit REG
|
||||
}
|
||||
|
||||
//================================================
|
||||
// WriteD8 - Write Memory To Double 8-bit (8-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD8(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//==================================================
|
||||
// WriteD16 - Write Memory To Double 8-bit (16-Bit)
|
||||
//==================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} + 1 // Load Source High Byte
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// WriteD8Index - Write Index To Double 8-bit (8-Bit)
|
||||
//====================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD8Index(REG, DEST) {
|
||||
t{REG}a // Transfer 8-Bit REG To 8-Bit A
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//======================================================
|
||||
// WriteD16Index - Write Index To Double 8-bit (16-Bit)
|
||||
//======================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD16Index(REG, DEST) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Transfer 16-Bit REG To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//=====================
|
||||
// SNES Initialisation
|
||||
//=====================
|
||||
// ROMSPEED: ROM Speed (SLOWROM, FASTROM)
|
||||
constant SLOWROM(0) // Access Cycle Designation (Slow ROM)
|
||||
constant FASTROM(1) // Access Cycle Designation (Fast ROM)
|
||||
macro SNES_INIT(ROMSPEED) {
|
||||
sei // Disable Interrupts
|
||||
clc // Clear Carry To Switch To Native Mode
|
||||
xce // Xchange Carry & Emulation Bit (Native Mode)
|
||||
|
||||
phk
|
||||
plb
|
||||
rep #$38
|
||||
|
||||
ldx.w #$1FFF // Set Stack To $1FFF
|
||||
txs // Transfer Index Register X To Stack Pointer
|
||||
|
||||
lda.w #$0000
|
||||
tcd
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
|
||||
lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1
|
||||
sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM)
|
||||
|
||||
lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness)
|
||||
sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100)
|
||||
|
||||
stz.w REG_OBSEL // Object Size & Object Base ($2101)
|
||||
stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102)
|
||||
stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103)
|
||||
stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105)
|
||||
stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106)
|
||||
stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107)
|
||||
stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108)
|
||||
stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109)
|
||||
stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A)
|
||||
stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B)
|
||||
stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114)
|
||||
|
||||
lda.b #$01
|
||||
stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B)
|
||||
sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D)
|
||||
stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E)
|
||||
sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120)
|
||||
|
||||
stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123)
|
||||
stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124)
|
||||
stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125)
|
||||
stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126)
|
||||
stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127)
|
||||
stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128)
|
||||
stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129)
|
||||
stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A)
|
||||
stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B)
|
||||
stz.w REG_TM // Main Screen Designation = 0 ($212C)
|
||||
stz.w REG_TS // Sub Screen Designation = 0 ($212D)
|
||||
stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E)
|
||||
stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F)
|
||||
|
||||
lda.b #$30
|
||||
sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130)
|
||||
stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131)
|
||||
|
||||
lda.b #$E0
|
||||
sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132)
|
||||
stz.w REG_SETINI // Display Control 2 = 0 ($2133)
|
||||
|
||||
stz.w REG_JOYWR // Joypad Output = 0 ($4016)
|
||||
|
||||
stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200)
|
||||
|
||||
lda.b #$FF
|
||||
sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201)
|
||||
|
||||
stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202)
|
||||
stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203)
|
||||
stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204)
|
||||
stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205)
|
||||
stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206)
|
||||
stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207)
|
||||
stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208)
|
||||
stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209)
|
||||
stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A)
|
||||
stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B)
|
||||
stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C)
|
||||
|
||||
// Clear OAM
|
||||
ldx.w #$0080
|
||||
lda.b #$E0
|
||||
-
|
||||
sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104)
|
||||
sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
ldx.w #$0020
|
||||
-
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
// Clear WRAM
|
||||
ldy.w #$0000
|
||||
sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181)
|
||||
stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183)
|
||||
|
||||
ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom
|
||||
lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank)
|
||||
stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302)
|
||||
sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
nop // Delay
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B)
|
||||
|
||||
// VRAM
|
||||
lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119)
|
||||
sta.w REG_VMAIN // VRAM Address Increment Mode ($2115)
|
||||
ldy.w #$0000
|
||||
sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
// CGRAM
|
||||
stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121)
|
||||
ldx.w #$200 // 512 Byte
|
||||
stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305)
|
||||
ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
jml +
|
||||
|
||||
CONST_ZERO:
|
||||
dw $0000
|
||||
|
||||
+
|
||||
}
|
||||
558
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/LIB/SNES_GFX.INC
Normal file
558
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/LIB/SNES_GFX.INC
Normal file
@ -0,0 +1,558 @@
|
||||
//===============
|
||||
// SNES Graphics
|
||||
//===============
|
||||
|
||||
//=============================
|
||||
// WaitNMI - Wait For NMI Flag
|
||||
//=============================
|
||||
macro WaitNMI() {
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
}
|
||||
|
||||
//======================================
|
||||
// WaitHV - Wait For H/V Timer IRQ Flag
|
||||
//======================================
|
||||
macro WaitHV() {
|
||||
-
|
||||
bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag
|
||||
bpl - // Wait For H/V Timer IRQ Flag
|
||||
}
|
||||
|
||||
//========================================
|
||||
// WaitHVB - Wait For V-Blank Period Flag
|
||||
//========================================
|
||||
macro WaitHVB() {
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
}
|
||||
|
||||
//================================================================
|
||||
// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing)
|
||||
//================================================================
|
||||
macro FadeIN() {
|
||||
ldx.w #$0000 // Set X To Mininmum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
inx // Increments Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$0F // Compare With Maximum Brightness Level (15)
|
||||
bne - // IF (Screen != Maximum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//=================================================================
|
||||
// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing)
|
||||
//=================================================================
|
||||
macro FadeOUT() {
|
||||
ldx.w #$000F // Set X To Maximum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
dex // Decrement Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$00 // Compare With Minimum Brightness Level
|
||||
bne - // IF (Screen != Minimum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//======================================
|
||||
// LoadPAL - Load Palette Data To CGRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadPAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==========================================
|
||||
// UpdatePAL - Update Palette Data To CGRAM
|
||||
//==========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdatePAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearLOVRAM - Clear VRAM Lo Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearHIVRAM - Clear VRAM Hi Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===================================
|
||||
// ClearVRAM - Clear VRAM Fixed Word
|
||||
//===================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
// Transfer Lo Byte
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Transfer Hi Byte
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==================================
|
||||
// LoadVRAM - Load GFX Data To VRAM
|
||||
//==================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================================
|
||||
// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride
|
||||
//========================================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// STRIDE: Dest Offset Stride
|
||||
// COUNT: Number Of DMA Transfers
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
-
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
txa // A = X
|
||||
clc // Clear Carry Flag
|
||||
adc.w #{STRIDE} >> 1
|
||||
tax // X = A
|
||||
lda.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1
|
||||
bne -
|
||||
}
|
||||
|
||||
//======================================
|
||||
// UpdateVRAM - Update GFX Data To VRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdateVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===========================================
|
||||
// LoadM7VRAM - Load Mode 7 GFX Data To VRAM
|
||||
//===========================================
|
||||
// SRCMAP: 24-Bit Address Of Source Map Data
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZEMAP: Size Of Map Data (BYTE Size)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) {
|
||||
// Load Mode7 Map Data To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCMAP} // Set Source Offset (Map)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCMAP} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map)
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset (Tiles)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8 - Scroll GFX BG From Memory (8-Bit)
|
||||
//===============================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8(BGSCR, BGPOS, DIR) {
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16 - Scroll GFX BG From Memory (16-Bit)
|
||||
//=================================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16(BGSCR, BGPOS, DIR) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
lda {BGSCR} + 1 // Load BG Scroll Position High Byte
|
||||
sta {BGPOS} // Store BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8I - Scroll GFX BG From Index (8-Bit)
|
||||
//===============================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
t{REG}a // Swaps 8-Bit Index To 8-Bit A
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16I - Scroll GFX BG From Index (16-Bit)
|
||||
//=================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Word
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Swaps 16-Bit Index To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {BGPOS} // Store A To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//======================================
|
||||
// Mode7CALC - Mode7 Matrix Calculation
|
||||
//======================================
|
||||
// A: Mode7 COS A Word
|
||||
// B: Mode7 SIN A Word
|
||||
// C: Mode7 SIN B Word
|
||||
// D: Mode7 COS B Word
|
||||
// ANGLE: Mode7 Angle Byte
|
||||
// SX: Mode7 Scale X Word
|
||||
// SY: Mode7 Scale Y Word
|
||||
// SINCOS: Mode7 SINCOS Table
|
||||
macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) {
|
||||
lda.b {ANGLE} // Load Angle To A
|
||||
tax // Transfer A To X
|
||||
|
||||
// Calculate B & C (SIN)
|
||||
// B
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {B}
|
||||
// C
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1 // High Byte
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
eor.b #$FF // Make Negative
|
||||
inc
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {C}
|
||||
|
||||
// Change X Index To Point To COS Values (X + 64)
|
||||
txa // Transfer X Index To A
|
||||
clc // Clear Carry Flag
|
||||
adc.b #64 // Add 64 With Carry
|
||||
tax // Transfer A To X Index
|
||||
|
||||
// Calculate A & D (COS)
|
||||
// A
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {A}
|
||||
// D
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {D}
|
||||
|
||||
// Store Result To Matrix
|
||||
lda.b {A}
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {A} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
|
||||
lda.b {B}
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
lda.b {B} + 1
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
|
||||
lda.b {C}
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
lda.b {C} + 1
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
|
||||
lda.b {D}
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
lda.b {D} + 1
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
//=============
|
||||
// SNES Header
|
||||
//=============
|
||||
seek($FFC0)
|
||||
// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes)
|
||||
db "65816 CPU TEST BIT "
|
||||
// "123456789012345678901"
|
||||
|
||||
// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode)
|
||||
db $20
|
||||
// ||___________________Map Mode:
|
||||
// | $X0 = LoROM/32K Banks (Mode 20)
|
||||
// | $X1 = HiROM/64K Banks (Mode 21)
|
||||
// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable)
|
||||
// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable)
|
||||
// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM)
|
||||
// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable)
|
||||
|
||||
// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type)
|
||||
db $00
|
||||
// ||___________________Type:
|
||||
// | $00 = ROM
|
||||
// | $01 = ROM+RAM
|
||||
// Co-processor: $02 = ROM+RAM+Battery
|
||||
// $0X = DSP $X3 = ROM+Co-processor
|
||||
// $1X = GSU $X4 = ROM+Co-processor+RAM
|
||||
// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery
|
||||
// $3X = SA-1 $X6 = ROM+Co-processor+Battery
|
||||
// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513
|
||||
// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked
|
||||
|
||||
// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits)
|
||||
db $01
|
||||
// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit)
|
||||
// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit)
|
||||
// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit)
|
||||
// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit)
|
||||
// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit)
|
||||
// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit)
|
||||
|
||||
// RAM SIZE
|
||||
db $00
|
||||
// $00 = None, $04 = 16Kb
|
||||
// $01 = 2Kb, $05 = 32Kb
|
||||
// $02 = 4Kb, $06 = 64Kb
|
||||
// $03 = 8Kb, $07 = 128Kb
|
||||
|
||||
// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz)
|
||||
db $00
|
||||
// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL)
|
||||
// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL)
|
||||
// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL)
|
||||
// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL)
|
||||
// $04 = Finland (PAL), $0D = South (K)orea (NTSC)
|
||||
// $05 = Denmark (PAL), $0E = (A)Common (ANY)
|
||||
// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC)
|
||||
// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M)
|
||||
// $08 = (S)pain (PAL), $11 = (U)Australia (PAL)
|
||||
|
||||
// DEVELOPER ID CODE
|
||||
db $00
|
||||
// $00 = None
|
||||
// $01 = Nintendo
|
||||
// $33 = New (Uses Extended Header)
|
||||
|
||||
// ROM VERSION NUMBER
|
||||
db $00
|
||||
// $00 = 1.00, $01 = 1.01
|
||||
|
||||
// COMPLEMENT CHECK
|
||||
db "CC"
|
||||
// CHECKSUM
|
||||
db "CS"
|
||||
|
||||
// NATIVE VECTOR (65C816 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (BRK Opcode)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $0000 // RESET VECTOR (Unused)
|
||||
dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt)
|
||||
|
||||
// EMU VECTOR (6502 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (Unused)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET)
|
||||
dw $0000 // IRQ/BRK VECTOR
|
||||
1
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/make.bat
Normal file
1
OSBindings/Mac/Clock SignalTests/krom 65816/BIT/make.bat
Normal file
@ -0,0 +1 @@
|
||||
bass CPUBIT.asm
|
||||
397
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/CPUBRA.asm
Normal file
397
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/CPUBRA.asm
Normal file
@ -0,0 +1,397 @@
|
||||
// SNES 65816 CPU Test BRA (Branch) demo by krom (Peter Lemon):
|
||||
arch snes.cpu
|
||||
output "CPUBRA.sfc", create
|
||||
|
||||
macro seek(variable offset) {
|
||||
origin ((offset & $7F0000) >> 1) | (offset & $7FFF)
|
||||
base offset
|
||||
}
|
||||
|
||||
macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
ldx.w #0 // X = 0 Number Of Text Characters To Print
|
||||
{#}LoopText:
|
||||
lda.w {SRC},x // A = Text Data
|
||||
sta.w REG_VMDATAL // Store Text To VRAM Lo Byte
|
||||
inx // X++
|
||||
cpx.w #{SIZE}
|
||||
bne {#}LoopText // IF (X != 0) Loop Text Characters
|
||||
}
|
||||
|
||||
macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM Address
|
||||
|
||||
lda.b #%10000000 // A = Negative Flag Bit
|
||||
jsr {#}PSRFlagTest // Test PSR Flag Data
|
||||
|
||||
lda.b #%01000000 // A = Overflow Flag Bit
|
||||
jsr {#}PSRFlagTest // Test PSR Flag Data
|
||||
|
||||
lda.b #%00000010 // A = Zero Flag Bit
|
||||
jsr {#}PSRFlagTest // Test PSR Flag Data
|
||||
|
||||
lda.b #%00000001 // A = Carry Flag Bit
|
||||
jsr {#}PSRFlagTest // Test PSR Flag Data
|
||||
|
||||
bra {#}PSREnd
|
||||
|
||||
{#}PSRFlagTest:
|
||||
bit.b {SRC} // Test Processor Status Flag Data Bit
|
||||
bne {#}PSRFlagSet
|
||||
lda.b #$30 // A = "0"
|
||||
sta.w REG_VMDATAL // Store Text To VRAM Lo Byte
|
||||
rts // Return From Subroutine
|
||||
{#}PSRFlagSet:
|
||||
lda.b #$31 // A = "1"
|
||||
sta.w REG_VMDATAL // Store Text To VRAM Lo Byte
|
||||
rts // Return From Subroutine
|
||||
|
||||
{#}PSREnd:
|
||||
}
|
||||
|
||||
seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes
|
||||
include "LIB/SNES.INC" // Include SNES Definitions
|
||||
include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table
|
||||
include "LIB/SNES_GFX.INC" // Include Graphics Macros
|
||||
|
||||
// Variable Data
|
||||
seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF)
|
||||
PSRFlagData:
|
||||
db 0 // Processor Status Register Flag Data Byte
|
||||
|
||||
seek($8000); Start:
|
||||
SNES_INIT(SLOWROM) // Run SNES Initialisation Routine
|
||||
|
||||
LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data
|
||||
LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles)
|
||||
ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word
|
||||
|
||||
// Setup Video
|
||||
lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size
|
||||
sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles
|
||||
|
||||
// Setup BG1 256 Color Background
|
||||
lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address
|
||||
sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400)
|
||||
lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address
|
||||
sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000)
|
||||
|
||||
lda.b #%00000001 // Enable BG1
|
||||
sta.w REG_TM // $212C: BG1 To Main Screen Designation
|
||||
|
||||
stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte
|
||||
stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte
|
||||
stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte
|
||||
stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte
|
||||
|
||||
lda.b #$F // Turn On Screen, Maximum Brightness
|
||||
sta.w REG_INIDISP // $2100: Screen Display
|
||||
|
||||
WaitNMI() // Wait For VSync
|
||||
|
||||
// Print Title Text
|
||||
PrintText(Title, $F882, 22) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Print Page Break Text
|
||||
PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Print Key Text
|
||||
PrintText(Key, $F942, 30) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Print Page Break Text
|
||||
PrintText(PageBreak, $F982, 30) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Type/Opcode Text
|
||||
PrintText(BCCBranch, $F9C2, 11) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
sep #$C3 // Set NVZC Flags
|
||||
clc // Clear Carry Flag
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Processor Status Flag Data
|
||||
PrintPSR(PSRFlagData, $F9E4) // Print Processor Status Flag Data
|
||||
|
||||
// Run Test
|
||||
clc // Clear Carry Flag
|
||||
bcc Pass1
|
||||
Fail1:
|
||||
PrintText(Fail, $F9F2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail1
|
||||
Pass1:
|
||||
PrintText(Pass, $F9F2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Type/Opcode Text
|
||||
PrintText(BCSBranch, $FA02, 11) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$C3 // Reset NVZC Flags
|
||||
sec // Set Carry Flag
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Processor Status Flag Data
|
||||
PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data
|
||||
|
||||
// Run Test
|
||||
sec // Set Carry Flag
|
||||
bcs Pass2
|
||||
Fail2:
|
||||
PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail2
|
||||
Pass2:
|
||||
PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Type/Opcode Text
|
||||
PrintText(BNEBranch, $FA42, 11) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
sep #$C3 // Set NVZC Flags
|
||||
rep #$02 // Reset Zero Flag
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Processor Status Flag Data
|
||||
PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data
|
||||
|
||||
// Run Test
|
||||
rep #$02 // Reset Zero Flag
|
||||
bne Pass3
|
||||
Fail3:
|
||||
PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail3
|
||||
Pass3:
|
||||
PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Type/Opcode Text
|
||||
PrintText(BEQBranch, $FA82, 11) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$C3 // Reset NVZC Flags
|
||||
sep #$02 // Set Zero Flag
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Processor Status Flag Data
|
||||
PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data
|
||||
|
||||
// Run Test
|
||||
sep #$02 // Set Zero Flag
|
||||
beq Pass4
|
||||
Fail4:
|
||||
PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail4
|
||||
Pass4:
|
||||
PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Type/Opcode Text
|
||||
PrintText(BVCBranch, $FAC2, 11) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
sep #$C3 // Set NVZC Flags
|
||||
clv // Clear Overflow Flag
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Processor Status Flag Data
|
||||
PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data
|
||||
|
||||
// Run Test
|
||||
clv // Clear Overflow Flag
|
||||
bvc Pass5
|
||||
Fail5:
|
||||
PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail5
|
||||
Pass5:
|
||||
PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Type/Opcode Text
|
||||
PrintText(BVSBranch, $FB02, 11) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$C3 // Reset NVZC Flags
|
||||
sep #$40 // Set Overflow Flag
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Processor Status Flag Data
|
||||
PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data
|
||||
|
||||
// Run Test
|
||||
sep #$40 // Set Overflow Flag
|
||||
bvs Pass6
|
||||
Fail6:
|
||||
PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail6
|
||||
Pass6:
|
||||
PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Type/Opcode Text
|
||||
PrintText(BPLBranch, $FB42, 11) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
sep #$C3 // Set NVZC Flags
|
||||
rep #$80 // Reset Negative Flag
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Processor Status Flag Data
|
||||
PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data
|
||||
|
||||
// Run Test
|
||||
rep #$80 // Reset Negative Flag
|
||||
bpl Pass7
|
||||
Fail7:
|
||||
PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail7
|
||||
Pass7:
|
||||
PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Type/Opcode Text
|
||||
PrintText(BMIBranch, $FB82, 11) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$C3 // Reset NVZC Flags
|
||||
sep #$80 // Set Negative Flag
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Processor Status Flag Data
|
||||
PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data
|
||||
|
||||
// Run Test
|
||||
sep #$80 // Set Negative Flag
|
||||
bmi Pass8
|
||||
Fail8:
|
||||
PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail8
|
||||
Pass8:
|
||||
PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Type/Opcode Text
|
||||
PrintText(BRABranch, $FBC2, 11) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$C3 // Reset NVZC Flags
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Processor Status Flag Data
|
||||
PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data
|
||||
|
||||
// Run Test
|
||||
bra Pass9
|
||||
Fail9:
|
||||
PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail9
|
||||
Pass9:
|
||||
PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// Print Type/Opcode Text
|
||||
PrintText(BRLBranch, $FC02, 11) // Load Text To VRAM Lo Bytes
|
||||
|
||||
// Setup Flags
|
||||
rep #$C3 // Reset NVZC Flags
|
||||
|
||||
// Store Processor Status Flag Data
|
||||
php // Push Processor Status Register To Stack
|
||||
pla // Pull Accumulator Register From Stack
|
||||
sta.b PSRFlagData // Store Processor Status Flag Data To Memory
|
||||
|
||||
// Print Processor Status Flag Data
|
||||
PrintPSR(PSRFlagData, $FC24) // Print Processor Status Flag Data
|
||||
|
||||
// Run Test
|
||||
brl Pass10
|
||||
Fail10:
|
||||
PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes
|
||||
bra Fail10
|
||||
Pass10:
|
||||
PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes
|
||||
|
||||
Loop:
|
||||
jmp Loop
|
||||
|
||||
Title:
|
||||
db "CPU Test BRA (Branch):"
|
||||
|
||||
PageBreak:
|
||||
db "------------------------------"
|
||||
|
||||
Key:
|
||||
db "Type | Opcode | NVZC | Test |"
|
||||
Fail:
|
||||
db "FAIL"
|
||||
Pass:
|
||||
db "PASS"
|
||||
|
||||
BCCBranch:
|
||||
db "BCC $90"
|
||||
BCSBranch:
|
||||
db "BCS $B0"
|
||||
BNEBranch:
|
||||
db "BNE $D0"
|
||||
BEQBranch:
|
||||
db "BEQ $F0"
|
||||
BVCBranch:
|
||||
db "BVC $50"
|
||||
BVSBranch:
|
||||
db "BVS $70"
|
||||
BPLBranch:
|
||||
db "BPL $10"
|
||||
BMIBranch:
|
||||
db "BMI $30"
|
||||
BRABranch:
|
||||
db "BRA $80"
|
||||
BRLBranch:
|
||||
db "BRL $82"
|
||||
|
||||
BGCHR:
|
||||
include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes)
|
||||
BGPAL:
|
||||
dw $7800, $7FFF // Blue / White Palette (4 Bytes)
|
||||
BGCLEAR:
|
||||
dw $0020 // BG Clear Character Space " " Fixed Word
|
||||
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/CPUBRA.png
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/CPUBRA.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.3 KiB |
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/CPUBRA.sfc
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/CPUBRA.sfc
Normal file
Binary file not shown.
957
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/Font8x8.asm
Normal file
957
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/Font8x8.asm
Normal file
@ -0,0 +1,957 @@
|
||||
fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes
|
||||
|
||||
// $20: Space " "
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $21: Exclamation mark "!"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $22: Quotation mark """
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $23: Cross hatch "#"
|
||||
db %00010100
|
||||
db %00010100
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $24: Dollar sign "$"
|
||||
db %00111100
|
||||
db %01101010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01010110
|
||||
db %00111100
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $25: Percent sign "%"
|
||||
db %00100010
|
||||
db %01010100
|
||||
db %00101000
|
||||
db %00010100
|
||||
db %00101010
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $26: Ampersand "&"
|
||||
db %00110000
|
||||
db %01001000
|
||||
db %00110010
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00110010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $27: Closing single quote "'"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $28: Opening parentheses "("
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
|
||||
// $29: Closing parentheses ")"
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
|
||||
// $2A: Asterisk "*"
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2B: Plus "+"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2C: Comma ","
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $2D: Hyphen "-"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2E: Period "."
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2F: Forward slash "/"
|
||||
db %00000010
|
||||
db %00000110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01100000
|
||||
db %01000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $30: 0
|
||||
db %00111010
|
||||
db %01100100
|
||||
db %01001010
|
||||
db %01010010
|
||||
db %00100110
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $31: 1
|
||||
db %00011000
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $32: 2
|
||||
db %00111000
|
||||
db %01001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $33: 3
|
||||
db %00111100
|
||||
db %01000110
|
||||
db %00011100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $34: 4
|
||||
db %00001100
|
||||
db %00011100
|
||||
db %00101100
|
||||
db %01001100
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $35: 5
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $36: 6
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $37: 7
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $38: 8
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $39: 9
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %00000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $3A: Colon ":"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3B: Semicolon ";"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $3C: Less than sign "<"
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3D: Equals sign "="
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3E: Greater than sign ">"
|
||||
db %00000000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3F: Question mark "?"
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
|
||||
// $40: At sign "@"
|
||||
db %01111100
|
||||
db %10000010
|
||||
db %10111010
|
||||
db %10101010
|
||||
db %10111110
|
||||
db %01000000
|
||||
db %00111110
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $41: A
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00100100
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $42: B
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $43: C
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $44: D
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $45: E
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $46: F
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $47: G
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $48: H
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $49: I
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4A: J
|
||||
db %00111110
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %01001100
|
||||
db %01111100
|
||||
db %00111000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4B: K
|
||||
db %01100110
|
||||
db %01101100
|
||||
db %01111000
|
||||
db %01111000
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4C: L
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4D: M
|
||||
db %01000010
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4E: N
|
||||
db %01000110
|
||||
db %01100110
|
||||
db %01110110
|
||||
db %01111110
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4F: O
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $50: P
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $51: Q
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100010
|
||||
db %01101010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $52: R
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $53: S
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $54: T
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $55: U
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $56: V
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00100100
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $57: W
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $58: X
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $59: Y
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5A: Z
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $5B: Opening square bracket "["
|
||||
db %00011100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011100
|
||||
|
||||
// $5C: Back slash "\"
|
||||
db %01000000
|
||||
db %01100000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00000110
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $5D: Closing square bracket "]"
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111000
|
||||
|
||||
// $5E: Caret "^"
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5F: Underscore "_"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %11111111
|
||||
|
||||
// $60: Opening single quote "`"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $61: a
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01100100
|
||||
db %01100100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $62: b
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00111100
|
||||
db %00110010
|
||||
db %00110010
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $63: c
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $64: d
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $65: e
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01101000
|
||||
db %01110010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $66: f
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011100
|
||||
db %00110010
|
||||
db %00110000
|
||||
db %01111100
|
||||
db %00110000
|
||||
db %00110000
|
||||
|
||||
// $67: g
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111010
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $68: h
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $69: i
|
||||
db %00110000
|
||||
db %00000000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6A: j
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $6B: k
|
||||
db %01100000
|
||||
db %01100100
|
||||
db %01101000
|
||||
db %01111000
|
||||
db %01100100
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6C: l
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6D: m
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01010100
|
||||
db %01101010
|
||||
db %01101010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6E: n
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6F: o
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $70: p
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
|
||||
// $71: q
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00110100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111100
|
||||
db %00001110
|
||||
db %00001100
|
||||
|
||||
// $72: r
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $73: s
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %00011000
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $74: t
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %01111000
|
||||
db %00110000
|
||||
db %00110010
|
||||
db %00011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $75: u
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $76: v
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $77: w
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %00101100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $78: x
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $79: y
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $7A: z
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $7B: Opening curly bracket "{"
|
||||
db %00011100
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011100
|
||||
|
||||
// $7C: Vertical line "|"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
|
||||
// $7D: Closing curly bracket "{"
|
||||
db %00111000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111000
|
||||
|
||||
// $7E: Tilde "~"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01110000
|
||||
db %01011010
|
||||
db %00001110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
507
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/LIB/SNES.INC
Normal file
507
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/LIB/SNES.INC
Normal file
@ -0,0 +1,507 @@
|
||||
//============== (Key: R=Read, W=Write, D=Double Read/Write)
|
||||
// SNES Include
|
||||
//==============
|
||||
// Memory Map
|
||||
constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW
|
||||
|
||||
// PPU Picture Processing Unit Ports (Write-Only)
|
||||
constant REG_INIDISP($2100) // Display Control 1 1B/W
|
||||
constant REG_OBSEL($2101) // Object Size & Object Base 1B/W
|
||||
constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W
|
||||
constant REG_OAMDATA($2104) // OAM Data Write 1B/W D
|
||||
constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W
|
||||
constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W
|
||||
constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W
|
||||
constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W
|
||||
constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D
|
||||
constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D
|
||||
constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W
|
||||
constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W
|
||||
constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W
|
||||
constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W
|
||||
constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W
|
||||
constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D
|
||||
constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D
|
||||
constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D
|
||||
constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D
|
||||
constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D
|
||||
constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D
|
||||
constant REG_CGADD($2121) // Palette CGRAM Address 1B/W
|
||||
constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D
|
||||
constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W
|
||||
constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W
|
||||
constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W
|
||||
constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W
|
||||
constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W
|
||||
constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W
|
||||
constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W
|
||||
constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W
|
||||
constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W
|
||||
constant REG_TM($212C) // Main Screen Designation 1B/W
|
||||
constant REG_TS($212D) // Sub Screen Designation 1B/W
|
||||
constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W
|
||||
constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W
|
||||
constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W
|
||||
constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W
|
||||
constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W
|
||||
constant REG_SETINI($2133) // Display Control 2 1B/W
|
||||
|
||||
// PPU Picture Processing Unit Ports (Read-Only)
|
||||
constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R
|
||||
constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R
|
||||
constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R
|
||||
constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R
|
||||
constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D
|
||||
constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R
|
||||
constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R
|
||||
constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D
|
||||
constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D
|
||||
constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D
|
||||
constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R
|
||||
constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R
|
||||
|
||||
// APU Audio Processing Unit Ports (Read/Write)
|
||||
constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW
|
||||
constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW
|
||||
constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW
|
||||
constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW
|
||||
// $2140..$2143 - APU Ports Mirrored To $2144..$217F
|
||||
|
||||
// WRAM Access Ports
|
||||
constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW
|
||||
constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W
|
||||
constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W
|
||||
constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W
|
||||
// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus)
|
||||
// $2200..$3FFF - Unused Region (A-Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz)
|
||||
// ($4000..$4015 - Unused Region (Open Bus)
|
||||
constant REG_JOYWR($4016) // Joypad Output 1B/W
|
||||
constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R
|
||||
constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R
|
||||
// $4018..$41FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Write-only, Read=Open Bus)
|
||||
constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W
|
||||
constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W
|
||||
constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W
|
||||
constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W
|
||||
constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W
|
||||
constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W
|
||||
constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W
|
||||
constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W
|
||||
constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W
|
||||
constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W
|
||||
constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W
|
||||
constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W
|
||||
// $420E..$420F - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Read-only)
|
||||
constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R
|
||||
constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R
|
||||
constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R
|
||||
constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R
|
||||
constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R
|
||||
constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R
|
||||
constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R
|
||||
constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R
|
||||
// $4220..$42FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port)
|
||||
constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW
|
||||
// $430C..$430E - Unused Region (Open Bus)
|
||||
constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW
|
||||
|
||||
constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW
|
||||
// $431C..$431E - Unused Region (Open Bus)
|
||||
constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW
|
||||
|
||||
constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW
|
||||
// $432C..$432E - Unused Region (Open Bus)
|
||||
constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW
|
||||
|
||||
constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW
|
||||
// $433C..$433E - Unused Region (Open Bus)
|
||||
constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW
|
||||
|
||||
constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW
|
||||
// $434C..$434E - Unused Region (Open Bus)
|
||||
constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW
|
||||
|
||||
constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW
|
||||
// $435C..$435E - Unused Region (Open Bus)
|
||||
constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW
|
||||
|
||||
constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW
|
||||
// $436C..$436E - Unused Region (Open Bus)
|
||||
constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW
|
||||
|
||||
constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW
|
||||
// $437C..$437E - Unused Region (Open Bus)
|
||||
constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW
|
||||
// $4380..$5FFF - Unused Region (Open Bus)
|
||||
|
||||
// Further Memory
|
||||
// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges)
|
||||
// $8000..$FFFF - Cartridge ROM
|
||||
|
||||
//================================================
|
||||
// ReadD16 - Read Double 8-bit To Memory (16-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro ReadD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} // Load Source High Byte
|
||||
sta {DEST} + 1 // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// ReadD16Index - Read Double 8-bit To Index (16-Bit)
|
||||
//====================================================
|
||||
// SRC: Source Address
|
||||
// REG: Destination Index Register (x, y)
|
||||
macro ReadD16Index(SRC, REG) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
lda {SRC} // Load Source High Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
ta{REG} // Transfer 16-Bit A To 16-Bit REG
|
||||
}
|
||||
|
||||
//================================================
|
||||
// WriteD8 - Write Memory To Double 8-bit (8-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD8(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//==================================================
|
||||
// WriteD16 - Write Memory To Double 8-bit (16-Bit)
|
||||
//==================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} + 1 // Load Source High Byte
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// WriteD8Index - Write Index To Double 8-bit (8-Bit)
|
||||
//====================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD8Index(REG, DEST) {
|
||||
t{REG}a // Transfer 8-Bit REG To 8-Bit A
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//======================================================
|
||||
// WriteD16Index - Write Index To Double 8-bit (16-Bit)
|
||||
//======================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD16Index(REG, DEST) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Transfer 16-Bit REG To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//=====================
|
||||
// SNES Initialisation
|
||||
//=====================
|
||||
// ROMSPEED: ROM Speed (SLOWROM, FASTROM)
|
||||
constant SLOWROM(0) // Access Cycle Designation (Slow ROM)
|
||||
constant FASTROM(1) // Access Cycle Designation (Fast ROM)
|
||||
macro SNES_INIT(ROMSPEED) {
|
||||
sei // Disable Interrupts
|
||||
clc // Clear Carry To Switch To Native Mode
|
||||
xce // Xchange Carry & Emulation Bit (Native Mode)
|
||||
|
||||
phk
|
||||
plb
|
||||
rep #$38
|
||||
|
||||
ldx.w #$1FFF // Set Stack To $1FFF
|
||||
txs // Transfer Index Register X To Stack Pointer
|
||||
|
||||
lda.w #$0000
|
||||
tcd
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
|
||||
lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1
|
||||
sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM)
|
||||
|
||||
lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness)
|
||||
sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100)
|
||||
|
||||
stz.w REG_OBSEL // Object Size & Object Base ($2101)
|
||||
stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102)
|
||||
stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103)
|
||||
stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105)
|
||||
stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106)
|
||||
stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107)
|
||||
stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108)
|
||||
stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109)
|
||||
stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A)
|
||||
stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B)
|
||||
stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114)
|
||||
|
||||
lda.b #$01
|
||||
stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B)
|
||||
sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D)
|
||||
stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E)
|
||||
sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120)
|
||||
|
||||
stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123)
|
||||
stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124)
|
||||
stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125)
|
||||
stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126)
|
||||
stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127)
|
||||
stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128)
|
||||
stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129)
|
||||
stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A)
|
||||
stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B)
|
||||
stz.w REG_TM // Main Screen Designation = 0 ($212C)
|
||||
stz.w REG_TS // Sub Screen Designation = 0 ($212D)
|
||||
stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E)
|
||||
stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F)
|
||||
|
||||
lda.b #$30
|
||||
sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130)
|
||||
stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131)
|
||||
|
||||
lda.b #$E0
|
||||
sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132)
|
||||
stz.w REG_SETINI // Display Control 2 = 0 ($2133)
|
||||
|
||||
stz.w REG_JOYWR // Joypad Output = 0 ($4016)
|
||||
|
||||
stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200)
|
||||
|
||||
lda.b #$FF
|
||||
sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201)
|
||||
|
||||
stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202)
|
||||
stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203)
|
||||
stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204)
|
||||
stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205)
|
||||
stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206)
|
||||
stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207)
|
||||
stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208)
|
||||
stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209)
|
||||
stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A)
|
||||
stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B)
|
||||
stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C)
|
||||
|
||||
// Clear OAM
|
||||
ldx.w #$0080
|
||||
lda.b #$E0
|
||||
-
|
||||
sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104)
|
||||
sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
ldx.w #$0020
|
||||
-
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
// Clear WRAM
|
||||
ldy.w #$0000
|
||||
sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181)
|
||||
stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183)
|
||||
|
||||
ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom
|
||||
lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank)
|
||||
stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302)
|
||||
sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
nop // Delay
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B)
|
||||
|
||||
// VRAM
|
||||
lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119)
|
||||
sta.w REG_VMAIN // VRAM Address Increment Mode ($2115)
|
||||
ldy.w #$0000
|
||||
sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
// CGRAM
|
||||
stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121)
|
||||
ldx.w #$200 // 512 Byte
|
||||
stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305)
|
||||
ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
jml +
|
||||
|
||||
CONST_ZERO:
|
||||
dw $0000
|
||||
|
||||
+
|
||||
}
|
||||
558
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/LIB/SNES_GFX.INC
Normal file
558
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/LIB/SNES_GFX.INC
Normal file
@ -0,0 +1,558 @@
|
||||
//===============
|
||||
// SNES Graphics
|
||||
//===============
|
||||
|
||||
//=============================
|
||||
// WaitNMI - Wait For NMI Flag
|
||||
//=============================
|
||||
macro WaitNMI() {
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
}
|
||||
|
||||
//======================================
|
||||
// WaitHV - Wait For H/V Timer IRQ Flag
|
||||
//======================================
|
||||
macro WaitHV() {
|
||||
-
|
||||
bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag
|
||||
bpl - // Wait For H/V Timer IRQ Flag
|
||||
}
|
||||
|
||||
//========================================
|
||||
// WaitHVB - Wait For V-Blank Period Flag
|
||||
//========================================
|
||||
macro WaitHVB() {
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
}
|
||||
|
||||
//================================================================
|
||||
// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing)
|
||||
//================================================================
|
||||
macro FadeIN() {
|
||||
ldx.w #$0000 // Set X To Mininmum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
inx // Increments Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$0F // Compare With Maximum Brightness Level (15)
|
||||
bne - // IF (Screen != Maximum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//=================================================================
|
||||
// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing)
|
||||
//=================================================================
|
||||
macro FadeOUT() {
|
||||
ldx.w #$000F // Set X To Maximum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
dex // Decrement Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$00 // Compare With Minimum Brightness Level
|
||||
bne - // IF (Screen != Minimum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//======================================
|
||||
// LoadPAL - Load Palette Data To CGRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadPAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==========================================
|
||||
// UpdatePAL - Update Palette Data To CGRAM
|
||||
//==========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdatePAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearLOVRAM - Clear VRAM Lo Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearHIVRAM - Clear VRAM Hi Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===================================
|
||||
// ClearVRAM - Clear VRAM Fixed Word
|
||||
//===================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
// Transfer Lo Byte
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Transfer Hi Byte
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==================================
|
||||
// LoadVRAM - Load GFX Data To VRAM
|
||||
//==================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================================
|
||||
// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride
|
||||
//========================================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// STRIDE: Dest Offset Stride
|
||||
// COUNT: Number Of DMA Transfers
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
-
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
txa // A = X
|
||||
clc // Clear Carry Flag
|
||||
adc.w #{STRIDE} >> 1
|
||||
tax // X = A
|
||||
lda.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1
|
||||
bne -
|
||||
}
|
||||
|
||||
//======================================
|
||||
// UpdateVRAM - Update GFX Data To VRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdateVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===========================================
|
||||
// LoadM7VRAM - Load Mode 7 GFX Data To VRAM
|
||||
//===========================================
|
||||
// SRCMAP: 24-Bit Address Of Source Map Data
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZEMAP: Size Of Map Data (BYTE Size)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) {
|
||||
// Load Mode7 Map Data To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCMAP} // Set Source Offset (Map)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCMAP} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map)
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset (Tiles)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8 - Scroll GFX BG From Memory (8-Bit)
|
||||
//===============================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8(BGSCR, BGPOS, DIR) {
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16 - Scroll GFX BG From Memory (16-Bit)
|
||||
//=================================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16(BGSCR, BGPOS, DIR) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
lda {BGSCR} + 1 // Load BG Scroll Position High Byte
|
||||
sta {BGPOS} // Store BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8I - Scroll GFX BG From Index (8-Bit)
|
||||
//===============================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
t{REG}a // Swaps 8-Bit Index To 8-Bit A
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16I - Scroll GFX BG From Index (16-Bit)
|
||||
//=================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Word
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Swaps 16-Bit Index To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {BGPOS} // Store A To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//======================================
|
||||
// Mode7CALC - Mode7 Matrix Calculation
|
||||
//======================================
|
||||
// A: Mode7 COS A Word
|
||||
// B: Mode7 SIN A Word
|
||||
// C: Mode7 SIN B Word
|
||||
// D: Mode7 COS B Word
|
||||
// ANGLE: Mode7 Angle Byte
|
||||
// SX: Mode7 Scale X Word
|
||||
// SY: Mode7 Scale Y Word
|
||||
// SINCOS: Mode7 SINCOS Table
|
||||
macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) {
|
||||
lda.b {ANGLE} // Load Angle To A
|
||||
tax // Transfer A To X
|
||||
|
||||
// Calculate B & C (SIN)
|
||||
// B
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {B}
|
||||
// C
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1 // High Byte
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
eor.b #$FF // Make Negative
|
||||
inc
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {C}
|
||||
|
||||
// Change X Index To Point To COS Values (X + 64)
|
||||
txa // Transfer X Index To A
|
||||
clc // Clear Carry Flag
|
||||
adc.b #64 // Add 64 With Carry
|
||||
tax // Transfer A To X Index
|
||||
|
||||
// Calculate A & D (COS)
|
||||
// A
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {A}
|
||||
// D
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {D}
|
||||
|
||||
// Store Result To Matrix
|
||||
lda.b {A}
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {A} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
|
||||
lda.b {B}
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
lda.b {B} + 1
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
|
||||
lda.b {C}
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
lda.b {C} + 1
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
|
||||
lda.b {D}
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
lda.b {D} + 1
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
//=============
|
||||
// SNES Header
|
||||
//=============
|
||||
seek($FFC0)
|
||||
// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes)
|
||||
db "65816 CPU TEST BRA "
|
||||
// "123456789012345678901"
|
||||
|
||||
// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode)
|
||||
db $20
|
||||
// ||___________________Map Mode:
|
||||
// | $X0 = LoROM/32K Banks (Mode 20)
|
||||
// | $X1 = HiROM/64K Banks (Mode 21)
|
||||
// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable)
|
||||
// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable)
|
||||
// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM)
|
||||
// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable)
|
||||
|
||||
// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type)
|
||||
db $00
|
||||
// ||___________________Type:
|
||||
// | $00 = ROM
|
||||
// | $01 = ROM+RAM
|
||||
// Co-processor: $02 = ROM+RAM+Battery
|
||||
// $0X = DSP $X3 = ROM+Co-processor
|
||||
// $1X = GSU $X4 = ROM+Co-processor+RAM
|
||||
// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery
|
||||
// $3X = SA-1 $X6 = ROM+Co-processor+Battery
|
||||
// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513
|
||||
// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked
|
||||
|
||||
// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits)
|
||||
db $01
|
||||
// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit)
|
||||
// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit)
|
||||
// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit)
|
||||
// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit)
|
||||
// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit)
|
||||
// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit)
|
||||
|
||||
// RAM SIZE
|
||||
db $00
|
||||
// $00 = None, $04 = 16Kb
|
||||
// $01 = 2Kb, $05 = 32Kb
|
||||
// $02 = 4Kb, $06 = 64Kb
|
||||
// $03 = 8Kb, $07 = 128Kb
|
||||
|
||||
// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz)
|
||||
db $00
|
||||
// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL)
|
||||
// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL)
|
||||
// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL)
|
||||
// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL)
|
||||
// $04 = Finland (PAL), $0D = South (K)orea (NTSC)
|
||||
// $05 = Denmark (PAL), $0E = (A)Common (ANY)
|
||||
// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC)
|
||||
// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M)
|
||||
// $08 = (S)pain (PAL), $11 = (U)Australia (PAL)
|
||||
|
||||
// DEVELOPER ID CODE
|
||||
db $00
|
||||
// $00 = None
|
||||
// $01 = Nintendo
|
||||
// $33 = New (Uses Extended Header)
|
||||
|
||||
// ROM VERSION NUMBER
|
||||
db $00
|
||||
// $00 = 1.00, $01 = 1.01
|
||||
|
||||
// COMPLEMENT CHECK
|
||||
db "CC"
|
||||
// CHECKSUM
|
||||
db "CS"
|
||||
|
||||
// NATIVE VECTOR (65C816 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (BRK Opcode)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $0000 // RESET VECTOR (Unused)
|
||||
dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt)
|
||||
|
||||
// EMU VECTOR (6502 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (Unused)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET)
|
||||
dw $0000 // IRQ/BRK VECTOR
|
||||
1
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/make.bat
Normal file
1
OSBindings/Mac/Clock SignalTests/krom 65816/BRA/make.bat
Normal file
@ -0,0 +1 @@
|
||||
bass CPUBRA.asm
|
||||
3694
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/CPUCMP.asm
Normal file
3694
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/CPUCMP.asm
Normal file
File diff suppressed because it is too large
Load Diff
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/CPUCMP.png
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/CPUCMP.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 1.9 KiB |
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/CPUCMP.sfc
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/CPUCMP.sfc
Normal file
Binary file not shown.
957
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/Font8x8.asm
Normal file
957
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/Font8x8.asm
Normal file
@ -0,0 +1,957 @@
|
||||
fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes
|
||||
|
||||
// $20: Space " "
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $21: Exclamation mark "!"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $22: Quotation mark """
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $23: Cross hatch "#"
|
||||
db %00010100
|
||||
db %00010100
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $24: Dollar sign "$"
|
||||
db %00111100
|
||||
db %01101010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01010110
|
||||
db %00111100
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $25: Percent sign "%"
|
||||
db %00100010
|
||||
db %01010100
|
||||
db %00101000
|
||||
db %00010100
|
||||
db %00101010
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $26: Ampersand "&"
|
||||
db %00110000
|
||||
db %01001000
|
||||
db %00110010
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00110010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $27: Closing single quote "'"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $28: Opening parentheses "("
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
|
||||
// $29: Closing parentheses ")"
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
|
||||
// $2A: Asterisk "*"
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2B: Plus "+"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2C: Comma ","
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $2D: Hyphen "-"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2E: Period "."
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2F: Forward slash "/"
|
||||
db %00000010
|
||||
db %00000110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01100000
|
||||
db %01000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $30: 0
|
||||
db %00111010
|
||||
db %01100100
|
||||
db %01001010
|
||||
db %01010010
|
||||
db %00100110
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $31: 1
|
||||
db %00011000
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $32: 2
|
||||
db %00111000
|
||||
db %01001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $33: 3
|
||||
db %00111100
|
||||
db %01000110
|
||||
db %00011100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $34: 4
|
||||
db %00001100
|
||||
db %00011100
|
||||
db %00101100
|
||||
db %01001100
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $35: 5
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $36: 6
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $37: 7
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $38: 8
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $39: 9
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %00000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $3A: Colon ":"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3B: Semicolon ";"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $3C: Less than sign "<"
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3D: Equals sign "="
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3E: Greater than sign ">"
|
||||
db %00000000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3F: Question mark "?"
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
|
||||
// $40: At sign "@"
|
||||
db %01111100
|
||||
db %10000010
|
||||
db %10111010
|
||||
db %10101010
|
||||
db %10111110
|
||||
db %01000000
|
||||
db %00111110
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $41: A
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00100100
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $42: B
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $43: C
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $44: D
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $45: E
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $46: F
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $47: G
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $48: H
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $49: I
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4A: J
|
||||
db %00111110
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %01001100
|
||||
db %01111100
|
||||
db %00111000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4B: K
|
||||
db %01100110
|
||||
db %01101100
|
||||
db %01111000
|
||||
db %01111000
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4C: L
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4D: M
|
||||
db %01000010
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4E: N
|
||||
db %01000110
|
||||
db %01100110
|
||||
db %01110110
|
||||
db %01111110
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4F: O
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $50: P
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $51: Q
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100010
|
||||
db %01101010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $52: R
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $53: S
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $54: T
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $55: U
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $56: V
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00100100
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $57: W
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $58: X
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $59: Y
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5A: Z
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $5B: Opening square bracket "["
|
||||
db %00011100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011100
|
||||
|
||||
// $5C: Back slash "\"
|
||||
db %01000000
|
||||
db %01100000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00000110
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $5D: Closing square bracket "]"
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111000
|
||||
|
||||
// $5E: Caret "^"
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5F: Underscore "_"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %11111111
|
||||
|
||||
// $60: Opening single quote "`"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $61: a
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01100100
|
||||
db %01100100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $62: b
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00111100
|
||||
db %00110010
|
||||
db %00110010
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $63: c
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $64: d
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $65: e
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01101000
|
||||
db %01110010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $66: f
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011100
|
||||
db %00110010
|
||||
db %00110000
|
||||
db %01111100
|
||||
db %00110000
|
||||
db %00110000
|
||||
|
||||
// $67: g
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111010
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $68: h
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $69: i
|
||||
db %00110000
|
||||
db %00000000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6A: j
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $6B: k
|
||||
db %01100000
|
||||
db %01100100
|
||||
db %01101000
|
||||
db %01111000
|
||||
db %01100100
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6C: l
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6D: m
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01010100
|
||||
db %01101010
|
||||
db %01101010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6E: n
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6F: o
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $70: p
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
|
||||
// $71: q
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00110100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111100
|
||||
db %00001110
|
||||
db %00001100
|
||||
|
||||
// $72: r
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $73: s
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %00011000
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $74: t
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %01111000
|
||||
db %00110000
|
||||
db %00110010
|
||||
db %00011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $75: u
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $76: v
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $77: w
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %00101100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $78: x
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $79: y
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $7A: z
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $7B: Opening curly bracket "{"
|
||||
db %00011100
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011100
|
||||
|
||||
// $7C: Vertical line "|"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
|
||||
// $7D: Closing curly bracket "{"
|
||||
db %00111000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111000
|
||||
|
||||
// $7E: Tilde "~"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01110000
|
||||
db %01011010
|
||||
db %00001110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
507
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/LIB/SNES.INC
Normal file
507
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/LIB/SNES.INC
Normal file
@ -0,0 +1,507 @@
|
||||
//============== (Key: R=Read, W=Write, D=Double Read/Write)
|
||||
// SNES Include
|
||||
//==============
|
||||
// Memory Map
|
||||
constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW
|
||||
|
||||
// PPU Picture Processing Unit Ports (Write-Only)
|
||||
constant REG_INIDISP($2100) // Display Control 1 1B/W
|
||||
constant REG_OBSEL($2101) // Object Size & Object Base 1B/W
|
||||
constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W
|
||||
constant REG_OAMDATA($2104) // OAM Data Write 1B/W D
|
||||
constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W
|
||||
constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W
|
||||
constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W
|
||||
constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W
|
||||
constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D
|
||||
constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D
|
||||
constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W
|
||||
constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W
|
||||
constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W
|
||||
constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W
|
||||
constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W
|
||||
constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D
|
||||
constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D
|
||||
constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D
|
||||
constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D
|
||||
constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D
|
||||
constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D
|
||||
constant REG_CGADD($2121) // Palette CGRAM Address 1B/W
|
||||
constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D
|
||||
constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W
|
||||
constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W
|
||||
constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W
|
||||
constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W
|
||||
constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W
|
||||
constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W
|
||||
constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W
|
||||
constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W
|
||||
constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W
|
||||
constant REG_TM($212C) // Main Screen Designation 1B/W
|
||||
constant REG_TS($212D) // Sub Screen Designation 1B/W
|
||||
constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W
|
||||
constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W
|
||||
constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W
|
||||
constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W
|
||||
constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W
|
||||
constant REG_SETINI($2133) // Display Control 2 1B/W
|
||||
|
||||
// PPU Picture Processing Unit Ports (Read-Only)
|
||||
constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R
|
||||
constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R
|
||||
constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R
|
||||
constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R
|
||||
constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D
|
||||
constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R
|
||||
constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R
|
||||
constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D
|
||||
constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D
|
||||
constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D
|
||||
constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R
|
||||
constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R
|
||||
|
||||
// APU Audio Processing Unit Ports (Read/Write)
|
||||
constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW
|
||||
constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW
|
||||
constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW
|
||||
constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW
|
||||
// $2140..$2143 - APU Ports Mirrored To $2144..$217F
|
||||
|
||||
// WRAM Access Ports
|
||||
constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW
|
||||
constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W
|
||||
constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W
|
||||
constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W
|
||||
// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus)
|
||||
// $2200..$3FFF - Unused Region (A-Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz)
|
||||
// ($4000..$4015 - Unused Region (Open Bus)
|
||||
constant REG_JOYWR($4016) // Joypad Output 1B/W
|
||||
constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R
|
||||
constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R
|
||||
// $4018..$41FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Write-only, Read=Open Bus)
|
||||
constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W
|
||||
constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W
|
||||
constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W
|
||||
constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W
|
||||
constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W
|
||||
constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W
|
||||
constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W
|
||||
constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W
|
||||
constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W
|
||||
constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W
|
||||
constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W
|
||||
constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W
|
||||
// $420E..$420F - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Read-only)
|
||||
constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R
|
||||
constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R
|
||||
constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R
|
||||
constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R
|
||||
constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R
|
||||
constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R
|
||||
constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R
|
||||
constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R
|
||||
// $4220..$42FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port)
|
||||
constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW
|
||||
// $430C..$430E - Unused Region (Open Bus)
|
||||
constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW
|
||||
|
||||
constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW
|
||||
// $431C..$431E - Unused Region (Open Bus)
|
||||
constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW
|
||||
|
||||
constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW
|
||||
// $432C..$432E - Unused Region (Open Bus)
|
||||
constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW
|
||||
|
||||
constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW
|
||||
// $433C..$433E - Unused Region (Open Bus)
|
||||
constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW
|
||||
|
||||
constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW
|
||||
// $434C..$434E - Unused Region (Open Bus)
|
||||
constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW
|
||||
|
||||
constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW
|
||||
// $435C..$435E - Unused Region (Open Bus)
|
||||
constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW
|
||||
|
||||
constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW
|
||||
// $436C..$436E - Unused Region (Open Bus)
|
||||
constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW
|
||||
|
||||
constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW
|
||||
// $437C..$437E - Unused Region (Open Bus)
|
||||
constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW
|
||||
// $4380..$5FFF - Unused Region (Open Bus)
|
||||
|
||||
// Further Memory
|
||||
// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges)
|
||||
// $8000..$FFFF - Cartridge ROM
|
||||
|
||||
//================================================
|
||||
// ReadD16 - Read Double 8-bit To Memory (16-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro ReadD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} // Load Source High Byte
|
||||
sta {DEST} + 1 // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// ReadD16Index - Read Double 8-bit To Index (16-Bit)
|
||||
//====================================================
|
||||
// SRC: Source Address
|
||||
// REG: Destination Index Register (x, y)
|
||||
macro ReadD16Index(SRC, REG) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
lda {SRC} // Load Source High Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
ta{REG} // Transfer 16-Bit A To 16-Bit REG
|
||||
}
|
||||
|
||||
//================================================
|
||||
// WriteD8 - Write Memory To Double 8-bit (8-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD8(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//==================================================
|
||||
// WriteD16 - Write Memory To Double 8-bit (16-Bit)
|
||||
//==================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} + 1 // Load Source High Byte
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// WriteD8Index - Write Index To Double 8-bit (8-Bit)
|
||||
//====================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD8Index(REG, DEST) {
|
||||
t{REG}a // Transfer 8-Bit REG To 8-Bit A
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//======================================================
|
||||
// WriteD16Index - Write Index To Double 8-bit (16-Bit)
|
||||
//======================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD16Index(REG, DEST) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Transfer 16-Bit REG To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//=====================
|
||||
// SNES Initialisation
|
||||
//=====================
|
||||
// ROMSPEED: ROM Speed (SLOWROM, FASTROM)
|
||||
constant SLOWROM(0) // Access Cycle Designation (Slow ROM)
|
||||
constant FASTROM(1) // Access Cycle Designation (Fast ROM)
|
||||
macro SNES_INIT(ROMSPEED) {
|
||||
sei // Disable Interrupts
|
||||
clc // Clear Carry To Switch To Native Mode
|
||||
xce // Xchange Carry & Emulation Bit (Native Mode)
|
||||
|
||||
phk
|
||||
plb
|
||||
rep #$38
|
||||
|
||||
ldx.w #$1FFF // Set Stack To $1FFF
|
||||
txs // Transfer Index Register X To Stack Pointer
|
||||
|
||||
lda.w #$0000
|
||||
tcd
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
|
||||
lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1
|
||||
sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM)
|
||||
|
||||
lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness)
|
||||
sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100)
|
||||
|
||||
stz.w REG_OBSEL // Object Size & Object Base ($2101)
|
||||
stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102)
|
||||
stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103)
|
||||
stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105)
|
||||
stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106)
|
||||
stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107)
|
||||
stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108)
|
||||
stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109)
|
||||
stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A)
|
||||
stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B)
|
||||
stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114)
|
||||
|
||||
lda.b #$01
|
||||
stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B)
|
||||
sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D)
|
||||
stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E)
|
||||
sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120)
|
||||
|
||||
stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123)
|
||||
stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124)
|
||||
stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125)
|
||||
stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126)
|
||||
stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127)
|
||||
stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128)
|
||||
stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129)
|
||||
stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A)
|
||||
stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B)
|
||||
stz.w REG_TM // Main Screen Designation = 0 ($212C)
|
||||
stz.w REG_TS // Sub Screen Designation = 0 ($212D)
|
||||
stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E)
|
||||
stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F)
|
||||
|
||||
lda.b #$30
|
||||
sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130)
|
||||
stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131)
|
||||
|
||||
lda.b #$E0
|
||||
sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132)
|
||||
stz.w REG_SETINI // Display Control 2 = 0 ($2133)
|
||||
|
||||
stz.w REG_JOYWR // Joypad Output = 0 ($4016)
|
||||
|
||||
stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200)
|
||||
|
||||
lda.b #$FF
|
||||
sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201)
|
||||
|
||||
stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202)
|
||||
stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203)
|
||||
stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204)
|
||||
stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205)
|
||||
stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206)
|
||||
stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207)
|
||||
stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208)
|
||||
stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209)
|
||||
stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A)
|
||||
stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B)
|
||||
stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C)
|
||||
|
||||
// Clear OAM
|
||||
ldx.w #$0080
|
||||
lda.b #$E0
|
||||
-
|
||||
sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104)
|
||||
sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
ldx.w #$0020
|
||||
-
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
// Clear WRAM
|
||||
ldy.w #$0000
|
||||
sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181)
|
||||
stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183)
|
||||
|
||||
ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom
|
||||
lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank)
|
||||
stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302)
|
||||
sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
nop // Delay
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B)
|
||||
|
||||
// VRAM
|
||||
lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119)
|
||||
sta.w REG_VMAIN // VRAM Address Increment Mode ($2115)
|
||||
ldy.w #$0000
|
||||
sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
// CGRAM
|
||||
stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121)
|
||||
ldx.w #$200 // 512 Byte
|
||||
stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305)
|
||||
ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
jml +
|
||||
|
||||
CONST_ZERO:
|
||||
dw $0000
|
||||
|
||||
+
|
||||
}
|
||||
558
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/LIB/SNES_GFX.INC
Normal file
558
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/LIB/SNES_GFX.INC
Normal file
@ -0,0 +1,558 @@
|
||||
//===============
|
||||
// SNES Graphics
|
||||
//===============
|
||||
|
||||
//=============================
|
||||
// WaitNMI - Wait For NMI Flag
|
||||
//=============================
|
||||
macro WaitNMI() {
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
}
|
||||
|
||||
//======================================
|
||||
// WaitHV - Wait For H/V Timer IRQ Flag
|
||||
//======================================
|
||||
macro WaitHV() {
|
||||
-
|
||||
bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag
|
||||
bpl - // Wait For H/V Timer IRQ Flag
|
||||
}
|
||||
|
||||
//========================================
|
||||
// WaitHVB - Wait For V-Blank Period Flag
|
||||
//========================================
|
||||
macro WaitHVB() {
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
}
|
||||
|
||||
//================================================================
|
||||
// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing)
|
||||
//================================================================
|
||||
macro FadeIN() {
|
||||
ldx.w #$0000 // Set X To Mininmum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
inx // Increments Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$0F // Compare With Maximum Brightness Level (15)
|
||||
bne - // IF (Screen != Maximum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//=================================================================
|
||||
// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing)
|
||||
//=================================================================
|
||||
macro FadeOUT() {
|
||||
ldx.w #$000F // Set X To Maximum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
dex // Decrement Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$00 // Compare With Minimum Brightness Level
|
||||
bne - // IF (Screen != Minimum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//======================================
|
||||
// LoadPAL - Load Palette Data To CGRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadPAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==========================================
|
||||
// UpdatePAL - Update Palette Data To CGRAM
|
||||
//==========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdatePAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearLOVRAM - Clear VRAM Lo Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearHIVRAM - Clear VRAM Hi Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===================================
|
||||
// ClearVRAM - Clear VRAM Fixed Word
|
||||
//===================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
// Transfer Lo Byte
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Transfer Hi Byte
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==================================
|
||||
// LoadVRAM - Load GFX Data To VRAM
|
||||
//==================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================================
|
||||
// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride
|
||||
//========================================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// STRIDE: Dest Offset Stride
|
||||
// COUNT: Number Of DMA Transfers
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
-
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
txa // A = X
|
||||
clc // Clear Carry Flag
|
||||
adc.w #{STRIDE} >> 1
|
||||
tax // X = A
|
||||
lda.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1
|
||||
bne -
|
||||
}
|
||||
|
||||
//======================================
|
||||
// UpdateVRAM - Update GFX Data To VRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdateVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===========================================
|
||||
// LoadM7VRAM - Load Mode 7 GFX Data To VRAM
|
||||
//===========================================
|
||||
// SRCMAP: 24-Bit Address Of Source Map Data
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZEMAP: Size Of Map Data (BYTE Size)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) {
|
||||
// Load Mode7 Map Data To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCMAP} // Set Source Offset (Map)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCMAP} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map)
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset (Tiles)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8 - Scroll GFX BG From Memory (8-Bit)
|
||||
//===============================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8(BGSCR, BGPOS, DIR) {
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16 - Scroll GFX BG From Memory (16-Bit)
|
||||
//=================================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16(BGSCR, BGPOS, DIR) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
lda {BGSCR} + 1 // Load BG Scroll Position High Byte
|
||||
sta {BGPOS} // Store BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8I - Scroll GFX BG From Index (8-Bit)
|
||||
//===============================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
t{REG}a // Swaps 8-Bit Index To 8-Bit A
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16I - Scroll GFX BG From Index (16-Bit)
|
||||
//=================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Word
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Swaps 16-Bit Index To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {BGPOS} // Store A To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//======================================
|
||||
// Mode7CALC - Mode7 Matrix Calculation
|
||||
//======================================
|
||||
// A: Mode7 COS A Word
|
||||
// B: Mode7 SIN A Word
|
||||
// C: Mode7 SIN B Word
|
||||
// D: Mode7 COS B Word
|
||||
// ANGLE: Mode7 Angle Byte
|
||||
// SX: Mode7 Scale X Word
|
||||
// SY: Mode7 Scale Y Word
|
||||
// SINCOS: Mode7 SINCOS Table
|
||||
macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) {
|
||||
lda.b {ANGLE} // Load Angle To A
|
||||
tax // Transfer A To X
|
||||
|
||||
// Calculate B & C (SIN)
|
||||
// B
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {B}
|
||||
// C
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1 // High Byte
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
eor.b #$FF // Make Negative
|
||||
inc
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {C}
|
||||
|
||||
// Change X Index To Point To COS Values (X + 64)
|
||||
txa // Transfer X Index To A
|
||||
clc // Clear Carry Flag
|
||||
adc.b #64 // Add 64 With Carry
|
||||
tax // Transfer A To X Index
|
||||
|
||||
// Calculate A & D (COS)
|
||||
// A
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {A}
|
||||
// D
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {D}
|
||||
|
||||
// Store Result To Matrix
|
||||
lda.b {A}
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {A} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
|
||||
lda.b {B}
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
lda.b {B} + 1
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
|
||||
lda.b {C}
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
lda.b {C} + 1
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
|
||||
lda.b {D}
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
lda.b {D} + 1
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
//=============
|
||||
// SNES Header
|
||||
//=============
|
||||
seek($FFC0)
|
||||
// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes)
|
||||
db "65816 CPU TEST CMP "
|
||||
// "123456789012345678901"
|
||||
|
||||
// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode)
|
||||
db $20
|
||||
// ||___________________Map Mode:
|
||||
// | $X0 = LoROM/32K Banks (Mode 20)
|
||||
// | $X1 = HiROM/64K Banks (Mode 21)
|
||||
// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable)
|
||||
// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable)
|
||||
// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM)
|
||||
// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable)
|
||||
|
||||
// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type)
|
||||
db $00
|
||||
// ||___________________Type:
|
||||
// | $00 = ROM
|
||||
// | $01 = ROM+RAM
|
||||
// Co-processor: $02 = ROM+RAM+Battery
|
||||
// $0X = DSP $X3 = ROM+Co-processor
|
||||
// $1X = GSU $X4 = ROM+Co-processor+RAM
|
||||
// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery
|
||||
// $3X = SA-1 $X6 = ROM+Co-processor+Battery
|
||||
// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513
|
||||
// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked
|
||||
|
||||
// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits)
|
||||
db $01
|
||||
// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit)
|
||||
// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit)
|
||||
// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit)
|
||||
// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit)
|
||||
// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit)
|
||||
// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit)
|
||||
|
||||
// RAM SIZE
|
||||
db $00
|
||||
// $00 = None, $04 = 16Kb
|
||||
// $01 = 2Kb, $05 = 32Kb
|
||||
// $02 = 4Kb, $06 = 64Kb
|
||||
// $03 = 8Kb, $07 = 128Kb
|
||||
|
||||
// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz)
|
||||
db $00
|
||||
// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL)
|
||||
// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL)
|
||||
// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL)
|
||||
// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL)
|
||||
// $04 = Finland (PAL), $0D = South (K)orea (NTSC)
|
||||
// $05 = Denmark (PAL), $0E = (A)Common (ANY)
|
||||
// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC)
|
||||
// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M)
|
||||
// $08 = (S)pain (PAL), $11 = (U)Australia (PAL)
|
||||
|
||||
// DEVELOPER ID CODE
|
||||
db $00
|
||||
// $00 = None
|
||||
// $01 = Nintendo
|
||||
// $33 = New (Uses Extended Header)
|
||||
|
||||
// ROM VERSION NUMBER
|
||||
db $00
|
||||
// $00 = 1.00, $01 = 1.01
|
||||
|
||||
// COMPLEMENT CHECK
|
||||
db "CC"
|
||||
// CHECKSUM
|
||||
db "CS"
|
||||
|
||||
// NATIVE VECTOR (65C816 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (BRK Opcode)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $0000 // RESET VECTOR (Unused)
|
||||
dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt)
|
||||
|
||||
// EMU VECTOR (6502 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (Unused)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET)
|
||||
dw $0000 // IRQ/BRK VECTOR
|
||||
1
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/make.bat
Normal file
1
OSBindings/Mac/Clock SignalTests/krom 65816/CMP/make.bat
Normal file
@ -0,0 +1 @@
|
||||
bass CPUCMP.asm
|
||||
1334
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/CPUDEC.asm
Normal file
1334
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/CPUDEC.asm
Normal file
File diff suppressed because it is too large
Load Diff
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/CPUDEC.png
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/CPUDEC.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.2 KiB |
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/CPUDEC.sfc
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/CPUDEC.sfc
Normal file
Binary file not shown.
957
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/Font8x8.asm
Normal file
957
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/Font8x8.asm
Normal file
@ -0,0 +1,957 @@
|
||||
fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes
|
||||
|
||||
// $20: Space " "
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $21: Exclamation mark "!"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $22: Quotation mark """
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $23: Cross hatch "#"
|
||||
db %00010100
|
||||
db %00010100
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $24: Dollar sign "$"
|
||||
db %00111100
|
||||
db %01101010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01010110
|
||||
db %00111100
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $25: Percent sign "%"
|
||||
db %00100010
|
||||
db %01010100
|
||||
db %00101000
|
||||
db %00010100
|
||||
db %00101010
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $26: Ampersand "&"
|
||||
db %00110000
|
||||
db %01001000
|
||||
db %00110010
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00110010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $27: Closing single quote "'"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $28: Opening parentheses "("
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
|
||||
// $29: Closing parentheses ")"
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
|
||||
// $2A: Asterisk "*"
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2B: Plus "+"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2C: Comma ","
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $2D: Hyphen "-"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2E: Period "."
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2F: Forward slash "/"
|
||||
db %00000010
|
||||
db %00000110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01100000
|
||||
db %01000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $30: 0
|
||||
db %00111010
|
||||
db %01100100
|
||||
db %01001010
|
||||
db %01010010
|
||||
db %00100110
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $31: 1
|
||||
db %00011000
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $32: 2
|
||||
db %00111000
|
||||
db %01001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $33: 3
|
||||
db %00111100
|
||||
db %01000110
|
||||
db %00011100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $34: 4
|
||||
db %00001100
|
||||
db %00011100
|
||||
db %00101100
|
||||
db %01001100
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $35: 5
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $36: 6
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $37: 7
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $38: 8
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $39: 9
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %00000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $3A: Colon ":"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3B: Semicolon ";"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $3C: Less than sign "<"
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3D: Equals sign "="
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3E: Greater than sign ">"
|
||||
db %00000000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3F: Question mark "?"
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
|
||||
// $40: At sign "@"
|
||||
db %01111100
|
||||
db %10000010
|
||||
db %10111010
|
||||
db %10101010
|
||||
db %10111110
|
||||
db %01000000
|
||||
db %00111110
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $41: A
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00100100
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $42: B
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $43: C
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $44: D
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $45: E
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $46: F
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $47: G
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $48: H
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $49: I
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4A: J
|
||||
db %00111110
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %01001100
|
||||
db %01111100
|
||||
db %00111000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4B: K
|
||||
db %01100110
|
||||
db %01101100
|
||||
db %01111000
|
||||
db %01111000
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4C: L
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4D: M
|
||||
db %01000010
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4E: N
|
||||
db %01000110
|
||||
db %01100110
|
||||
db %01110110
|
||||
db %01111110
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4F: O
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $50: P
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $51: Q
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100010
|
||||
db %01101010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $52: R
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $53: S
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $54: T
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $55: U
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $56: V
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00100100
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $57: W
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $58: X
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $59: Y
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5A: Z
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $5B: Opening square bracket "["
|
||||
db %00011100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011100
|
||||
|
||||
// $5C: Back slash "\"
|
||||
db %01000000
|
||||
db %01100000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00000110
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $5D: Closing square bracket "]"
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111000
|
||||
|
||||
// $5E: Caret "^"
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5F: Underscore "_"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %11111111
|
||||
|
||||
// $60: Opening single quote "`"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $61: a
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01100100
|
||||
db %01100100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $62: b
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00111100
|
||||
db %00110010
|
||||
db %00110010
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $63: c
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $64: d
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $65: e
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01101000
|
||||
db %01110010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $66: f
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011100
|
||||
db %00110010
|
||||
db %00110000
|
||||
db %01111100
|
||||
db %00110000
|
||||
db %00110000
|
||||
|
||||
// $67: g
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111010
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $68: h
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $69: i
|
||||
db %00110000
|
||||
db %00000000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6A: j
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $6B: k
|
||||
db %01100000
|
||||
db %01100100
|
||||
db %01101000
|
||||
db %01111000
|
||||
db %01100100
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6C: l
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6D: m
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01010100
|
||||
db %01101010
|
||||
db %01101010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6E: n
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6F: o
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $70: p
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
|
||||
// $71: q
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00110100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111100
|
||||
db %00001110
|
||||
db %00001100
|
||||
|
||||
// $72: r
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $73: s
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %00011000
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $74: t
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %01111000
|
||||
db %00110000
|
||||
db %00110010
|
||||
db %00011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $75: u
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $76: v
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $77: w
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %00101100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $78: x
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $79: y
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $7A: z
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $7B: Opening curly bracket "{"
|
||||
db %00011100
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011100
|
||||
|
||||
// $7C: Vertical line "|"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
|
||||
// $7D: Closing curly bracket "{"
|
||||
db %00111000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111000
|
||||
|
||||
// $7E: Tilde "~"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01110000
|
||||
db %01011010
|
||||
db %00001110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
507
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/LIB/SNES.INC
Normal file
507
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/LIB/SNES.INC
Normal file
@ -0,0 +1,507 @@
|
||||
//============== (Key: R=Read, W=Write, D=Double Read/Write)
|
||||
// SNES Include
|
||||
//==============
|
||||
// Memory Map
|
||||
constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW
|
||||
|
||||
// PPU Picture Processing Unit Ports (Write-Only)
|
||||
constant REG_INIDISP($2100) // Display Control 1 1B/W
|
||||
constant REG_OBSEL($2101) // Object Size & Object Base 1B/W
|
||||
constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W
|
||||
constant REG_OAMDATA($2104) // OAM Data Write 1B/W D
|
||||
constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W
|
||||
constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W
|
||||
constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W
|
||||
constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W
|
||||
constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D
|
||||
constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D
|
||||
constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W
|
||||
constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W
|
||||
constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W
|
||||
constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W
|
||||
constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W
|
||||
constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D
|
||||
constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D
|
||||
constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D
|
||||
constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D
|
||||
constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D
|
||||
constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D
|
||||
constant REG_CGADD($2121) // Palette CGRAM Address 1B/W
|
||||
constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D
|
||||
constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W
|
||||
constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W
|
||||
constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W
|
||||
constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W
|
||||
constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W
|
||||
constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W
|
||||
constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W
|
||||
constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W
|
||||
constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W
|
||||
constant REG_TM($212C) // Main Screen Designation 1B/W
|
||||
constant REG_TS($212D) // Sub Screen Designation 1B/W
|
||||
constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W
|
||||
constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W
|
||||
constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W
|
||||
constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W
|
||||
constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W
|
||||
constant REG_SETINI($2133) // Display Control 2 1B/W
|
||||
|
||||
// PPU Picture Processing Unit Ports (Read-Only)
|
||||
constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R
|
||||
constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R
|
||||
constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R
|
||||
constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R
|
||||
constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D
|
||||
constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R
|
||||
constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R
|
||||
constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D
|
||||
constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D
|
||||
constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D
|
||||
constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R
|
||||
constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R
|
||||
|
||||
// APU Audio Processing Unit Ports (Read/Write)
|
||||
constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW
|
||||
constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW
|
||||
constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW
|
||||
constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW
|
||||
// $2140..$2143 - APU Ports Mirrored To $2144..$217F
|
||||
|
||||
// WRAM Access Ports
|
||||
constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW
|
||||
constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W
|
||||
constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W
|
||||
constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W
|
||||
// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus)
|
||||
// $2200..$3FFF - Unused Region (A-Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz)
|
||||
// ($4000..$4015 - Unused Region (Open Bus)
|
||||
constant REG_JOYWR($4016) // Joypad Output 1B/W
|
||||
constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R
|
||||
constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R
|
||||
// $4018..$41FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Write-only, Read=Open Bus)
|
||||
constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W
|
||||
constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W
|
||||
constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W
|
||||
constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W
|
||||
constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W
|
||||
constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W
|
||||
constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W
|
||||
constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W
|
||||
constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W
|
||||
constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W
|
||||
constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W
|
||||
constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W
|
||||
// $420E..$420F - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Read-only)
|
||||
constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R
|
||||
constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R
|
||||
constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R
|
||||
constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R
|
||||
constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R
|
||||
constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R
|
||||
constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R
|
||||
constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R
|
||||
// $4220..$42FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port)
|
||||
constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW
|
||||
// $430C..$430E - Unused Region (Open Bus)
|
||||
constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW
|
||||
|
||||
constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW
|
||||
// $431C..$431E - Unused Region (Open Bus)
|
||||
constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW
|
||||
|
||||
constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW
|
||||
// $432C..$432E - Unused Region (Open Bus)
|
||||
constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW
|
||||
|
||||
constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW
|
||||
// $433C..$433E - Unused Region (Open Bus)
|
||||
constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW
|
||||
|
||||
constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW
|
||||
// $434C..$434E - Unused Region (Open Bus)
|
||||
constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW
|
||||
|
||||
constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW
|
||||
// $435C..$435E - Unused Region (Open Bus)
|
||||
constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW
|
||||
|
||||
constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW
|
||||
// $436C..$436E - Unused Region (Open Bus)
|
||||
constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW
|
||||
|
||||
constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW
|
||||
// $437C..$437E - Unused Region (Open Bus)
|
||||
constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW
|
||||
// $4380..$5FFF - Unused Region (Open Bus)
|
||||
|
||||
// Further Memory
|
||||
// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges)
|
||||
// $8000..$FFFF - Cartridge ROM
|
||||
|
||||
//================================================
|
||||
// ReadD16 - Read Double 8-bit To Memory (16-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro ReadD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} // Load Source High Byte
|
||||
sta {DEST} + 1 // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// ReadD16Index - Read Double 8-bit To Index (16-Bit)
|
||||
//====================================================
|
||||
// SRC: Source Address
|
||||
// REG: Destination Index Register (x, y)
|
||||
macro ReadD16Index(SRC, REG) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
lda {SRC} // Load Source High Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
ta{REG} // Transfer 16-Bit A To 16-Bit REG
|
||||
}
|
||||
|
||||
//================================================
|
||||
// WriteD8 - Write Memory To Double 8-bit (8-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD8(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//==================================================
|
||||
// WriteD16 - Write Memory To Double 8-bit (16-Bit)
|
||||
//==================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} + 1 // Load Source High Byte
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// WriteD8Index - Write Index To Double 8-bit (8-Bit)
|
||||
//====================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD8Index(REG, DEST) {
|
||||
t{REG}a // Transfer 8-Bit REG To 8-Bit A
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//======================================================
|
||||
// WriteD16Index - Write Index To Double 8-bit (16-Bit)
|
||||
//======================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD16Index(REG, DEST) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Transfer 16-Bit REG To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//=====================
|
||||
// SNES Initialisation
|
||||
//=====================
|
||||
// ROMSPEED: ROM Speed (SLOWROM, FASTROM)
|
||||
constant SLOWROM(0) // Access Cycle Designation (Slow ROM)
|
||||
constant FASTROM(1) // Access Cycle Designation (Fast ROM)
|
||||
macro SNES_INIT(ROMSPEED) {
|
||||
sei // Disable Interrupts
|
||||
clc // Clear Carry To Switch To Native Mode
|
||||
xce // Xchange Carry & Emulation Bit (Native Mode)
|
||||
|
||||
phk
|
||||
plb
|
||||
rep #$38
|
||||
|
||||
ldx.w #$1FFF // Set Stack To $1FFF
|
||||
txs // Transfer Index Register X To Stack Pointer
|
||||
|
||||
lda.w #$0000
|
||||
tcd
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
|
||||
lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1
|
||||
sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM)
|
||||
|
||||
lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness)
|
||||
sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100)
|
||||
|
||||
stz.w REG_OBSEL // Object Size & Object Base ($2101)
|
||||
stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102)
|
||||
stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103)
|
||||
stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105)
|
||||
stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106)
|
||||
stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107)
|
||||
stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108)
|
||||
stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109)
|
||||
stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A)
|
||||
stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B)
|
||||
stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114)
|
||||
|
||||
lda.b #$01
|
||||
stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B)
|
||||
sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D)
|
||||
stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E)
|
||||
sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120)
|
||||
|
||||
stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123)
|
||||
stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124)
|
||||
stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125)
|
||||
stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126)
|
||||
stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127)
|
||||
stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128)
|
||||
stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129)
|
||||
stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A)
|
||||
stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B)
|
||||
stz.w REG_TM // Main Screen Designation = 0 ($212C)
|
||||
stz.w REG_TS // Sub Screen Designation = 0 ($212D)
|
||||
stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E)
|
||||
stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F)
|
||||
|
||||
lda.b #$30
|
||||
sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130)
|
||||
stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131)
|
||||
|
||||
lda.b #$E0
|
||||
sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132)
|
||||
stz.w REG_SETINI // Display Control 2 = 0 ($2133)
|
||||
|
||||
stz.w REG_JOYWR // Joypad Output = 0 ($4016)
|
||||
|
||||
stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200)
|
||||
|
||||
lda.b #$FF
|
||||
sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201)
|
||||
|
||||
stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202)
|
||||
stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203)
|
||||
stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204)
|
||||
stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205)
|
||||
stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206)
|
||||
stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207)
|
||||
stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208)
|
||||
stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209)
|
||||
stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A)
|
||||
stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B)
|
||||
stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C)
|
||||
|
||||
// Clear OAM
|
||||
ldx.w #$0080
|
||||
lda.b #$E0
|
||||
-
|
||||
sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104)
|
||||
sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
ldx.w #$0020
|
||||
-
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
// Clear WRAM
|
||||
ldy.w #$0000
|
||||
sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181)
|
||||
stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183)
|
||||
|
||||
ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom
|
||||
lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank)
|
||||
stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302)
|
||||
sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
nop // Delay
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B)
|
||||
|
||||
// VRAM
|
||||
lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119)
|
||||
sta.w REG_VMAIN // VRAM Address Increment Mode ($2115)
|
||||
ldy.w #$0000
|
||||
sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
// CGRAM
|
||||
stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121)
|
||||
ldx.w #$200 // 512 Byte
|
||||
stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305)
|
||||
ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
jml +
|
||||
|
||||
CONST_ZERO:
|
||||
dw $0000
|
||||
|
||||
+
|
||||
}
|
||||
558
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/LIB/SNES_GFX.INC
Normal file
558
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/LIB/SNES_GFX.INC
Normal file
@ -0,0 +1,558 @@
|
||||
//===============
|
||||
// SNES Graphics
|
||||
//===============
|
||||
|
||||
//=============================
|
||||
// WaitNMI - Wait For NMI Flag
|
||||
//=============================
|
||||
macro WaitNMI() {
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
}
|
||||
|
||||
//======================================
|
||||
// WaitHV - Wait For H/V Timer IRQ Flag
|
||||
//======================================
|
||||
macro WaitHV() {
|
||||
-
|
||||
bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag
|
||||
bpl - // Wait For H/V Timer IRQ Flag
|
||||
}
|
||||
|
||||
//========================================
|
||||
// WaitHVB - Wait For V-Blank Period Flag
|
||||
//========================================
|
||||
macro WaitHVB() {
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
}
|
||||
|
||||
//================================================================
|
||||
// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing)
|
||||
//================================================================
|
||||
macro FadeIN() {
|
||||
ldx.w #$0000 // Set X To Mininmum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
inx // Increments Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$0F // Compare With Maximum Brightness Level (15)
|
||||
bne - // IF (Screen != Maximum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//=================================================================
|
||||
// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing)
|
||||
//=================================================================
|
||||
macro FadeOUT() {
|
||||
ldx.w #$000F // Set X To Maximum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
dex // Decrement Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$00 // Compare With Minimum Brightness Level
|
||||
bne - // IF (Screen != Minimum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//======================================
|
||||
// LoadPAL - Load Palette Data To CGRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadPAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==========================================
|
||||
// UpdatePAL - Update Palette Data To CGRAM
|
||||
//==========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdatePAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearLOVRAM - Clear VRAM Lo Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearHIVRAM - Clear VRAM Hi Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===================================
|
||||
// ClearVRAM - Clear VRAM Fixed Word
|
||||
//===================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
// Transfer Lo Byte
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Transfer Hi Byte
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==================================
|
||||
// LoadVRAM - Load GFX Data To VRAM
|
||||
//==================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================================
|
||||
// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride
|
||||
//========================================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// STRIDE: Dest Offset Stride
|
||||
// COUNT: Number Of DMA Transfers
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
-
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
txa // A = X
|
||||
clc // Clear Carry Flag
|
||||
adc.w #{STRIDE} >> 1
|
||||
tax // X = A
|
||||
lda.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1
|
||||
bne -
|
||||
}
|
||||
|
||||
//======================================
|
||||
// UpdateVRAM - Update GFX Data To VRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdateVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===========================================
|
||||
// LoadM7VRAM - Load Mode 7 GFX Data To VRAM
|
||||
//===========================================
|
||||
// SRCMAP: 24-Bit Address Of Source Map Data
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZEMAP: Size Of Map Data (BYTE Size)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) {
|
||||
// Load Mode7 Map Data To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCMAP} // Set Source Offset (Map)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCMAP} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map)
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset (Tiles)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8 - Scroll GFX BG From Memory (8-Bit)
|
||||
//===============================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8(BGSCR, BGPOS, DIR) {
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16 - Scroll GFX BG From Memory (16-Bit)
|
||||
//=================================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16(BGSCR, BGPOS, DIR) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
lda {BGSCR} + 1 // Load BG Scroll Position High Byte
|
||||
sta {BGPOS} // Store BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8I - Scroll GFX BG From Index (8-Bit)
|
||||
//===============================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
t{REG}a // Swaps 8-Bit Index To 8-Bit A
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16I - Scroll GFX BG From Index (16-Bit)
|
||||
//=================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Word
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Swaps 16-Bit Index To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {BGPOS} // Store A To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//======================================
|
||||
// Mode7CALC - Mode7 Matrix Calculation
|
||||
//======================================
|
||||
// A: Mode7 COS A Word
|
||||
// B: Mode7 SIN A Word
|
||||
// C: Mode7 SIN B Word
|
||||
// D: Mode7 COS B Word
|
||||
// ANGLE: Mode7 Angle Byte
|
||||
// SX: Mode7 Scale X Word
|
||||
// SY: Mode7 Scale Y Word
|
||||
// SINCOS: Mode7 SINCOS Table
|
||||
macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) {
|
||||
lda.b {ANGLE} // Load Angle To A
|
||||
tax // Transfer A To X
|
||||
|
||||
// Calculate B & C (SIN)
|
||||
// B
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {B}
|
||||
// C
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1 // High Byte
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
eor.b #$FF // Make Negative
|
||||
inc
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {C}
|
||||
|
||||
// Change X Index To Point To COS Values (X + 64)
|
||||
txa // Transfer X Index To A
|
||||
clc // Clear Carry Flag
|
||||
adc.b #64 // Add 64 With Carry
|
||||
tax // Transfer A To X Index
|
||||
|
||||
// Calculate A & D (COS)
|
||||
// A
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {A}
|
||||
// D
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {D}
|
||||
|
||||
// Store Result To Matrix
|
||||
lda.b {A}
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {A} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
|
||||
lda.b {B}
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
lda.b {B} + 1
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
|
||||
lda.b {C}
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
lda.b {C} + 1
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
|
||||
lda.b {D}
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
lda.b {D} + 1
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
//=============
|
||||
// SNES Header
|
||||
//=============
|
||||
seek($FFC0)
|
||||
// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes)
|
||||
db "65816 CPU TEST DEC "
|
||||
// "123456789012345678901"
|
||||
|
||||
// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode)
|
||||
db $20
|
||||
// ||___________________Map Mode:
|
||||
// | $X0 = LoROM/32K Banks (Mode 20)
|
||||
// | $X1 = HiROM/64K Banks (Mode 21)
|
||||
// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable)
|
||||
// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable)
|
||||
// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM)
|
||||
// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable)
|
||||
|
||||
// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type)
|
||||
db $00
|
||||
// ||___________________Type:
|
||||
// | $00 = ROM
|
||||
// | $01 = ROM+RAM
|
||||
// Co-processor: $02 = ROM+RAM+Battery
|
||||
// $0X = DSP $X3 = ROM+Co-processor
|
||||
// $1X = GSU $X4 = ROM+Co-processor+RAM
|
||||
// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery
|
||||
// $3X = SA-1 $X6 = ROM+Co-processor+Battery
|
||||
// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513
|
||||
// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked
|
||||
|
||||
// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits)
|
||||
db $01
|
||||
// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit)
|
||||
// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit)
|
||||
// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit)
|
||||
// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit)
|
||||
// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit)
|
||||
// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit)
|
||||
|
||||
// RAM SIZE
|
||||
db $00
|
||||
// $00 = None, $04 = 16Kb
|
||||
// $01 = 2Kb, $05 = 32Kb
|
||||
// $02 = 4Kb, $06 = 64Kb
|
||||
// $03 = 8Kb, $07 = 128Kb
|
||||
|
||||
// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz)
|
||||
db $00
|
||||
// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL)
|
||||
// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL)
|
||||
// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL)
|
||||
// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL)
|
||||
// $04 = Finland (PAL), $0D = South (K)orea (NTSC)
|
||||
// $05 = Denmark (PAL), $0E = (A)Common (ANY)
|
||||
// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC)
|
||||
// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M)
|
||||
// $08 = (S)pain (PAL), $11 = (U)Australia (PAL)
|
||||
|
||||
// DEVELOPER ID CODE
|
||||
db $00
|
||||
// $00 = None
|
||||
// $01 = Nintendo
|
||||
// $33 = New (Uses Extended Header)
|
||||
|
||||
// ROM VERSION NUMBER
|
||||
db $00
|
||||
// $00 = 1.00, $01 = 1.01
|
||||
|
||||
// COMPLEMENT CHECK
|
||||
db "CC"
|
||||
// CHECKSUM
|
||||
db "CS"
|
||||
|
||||
// NATIVE VECTOR (65C816 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (BRK Opcode)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $0000 // RESET VECTOR (Unused)
|
||||
dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt)
|
||||
|
||||
// EMU VECTOR (6502 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (Unused)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET)
|
||||
dw $0000 // IRQ/BRK VECTOR
|
||||
1
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/make.bat
Normal file
1
OSBindings/Mac/Clock SignalTests/krom 65816/DEC/make.bat
Normal file
@ -0,0 +1 @@
|
||||
bass CPUDEC.asm
|
||||
2772
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/CPUEOR.asm
Normal file
2772
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/CPUEOR.asm
Normal file
File diff suppressed because it is too large
Load Diff
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/CPUEOR.png
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/CPUEOR.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.0 KiB |
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/CPUEOR.sfc
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/CPUEOR.sfc
Normal file
Binary file not shown.
957
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/Font8x8.asm
Normal file
957
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/Font8x8.asm
Normal file
@ -0,0 +1,957 @@
|
||||
fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes
|
||||
|
||||
// $20: Space " "
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $21: Exclamation mark "!"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $22: Quotation mark """
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $23: Cross hatch "#"
|
||||
db %00010100
|
||||
db %00010100
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $24: Dollar sign "$"
|
||||
db %00111100
|
||||
db %01101010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01010110
|
||||
db %00111100
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $25: Percent sign "%"
|
||||
db %00100010
|
||||
db %01010100
|
||||
db %00101000
|
||||
db %00010100
|
||||
db %00101010
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $26: Ampersand "&"
|
||||
db %00110000
|
||||
db %01001000
|
||||
db %00110010
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00110010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $27: Closing single quote "'"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $28: Opening parentheses "("
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
|
||||
// $29: Closing parentheses ")"
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
|
||||
// $2A: Asterisk "*"
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2B: Plus "+"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2C: Comma ","
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $2D: Hyphen "-"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2E: Period "."
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2F: Forward slash "/"
|
||||
db %00000010
|
||||
db %00000110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01100000
|
||||
db %01000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $30: 0
|
||||
db %00111010
|
||||
db %01100100
|
||||
db %01001010
|
||||
db %01010010
|
||||
db %00100110
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $31: 1
|
||||
db %00011000
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $32: 2
|
||||
db %00111000
|
||||
db %01001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $33: 3
|
||||
db %00111100
|
||||
db %01000110
|
||||
db %00011100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $34: 4
|
||||
db %00001100
|
||||
db %00011100
|
||||
db %00101100
|
||||
db %01001100
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $35: 5
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $36: 6
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $37: 7
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $38: 8
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $39: 9
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %00000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $3A: Colon ":"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3B: Semicolon ";"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $3C: Less than sign "<"
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3D: Equals sign "="
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3E: Greater than sign ">"
|
||||
db %00000000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3F: Question mark "?"
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
|
||||
// $40: At sign "@"
|
||||
db %01111100
|
||||
db %10000010
|
||||
db %10111010
|
||||
db %10101010
|
||||
db %10111110
|
||||
db %01000000
|
||||
db %00111110
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $41: A
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00100100
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $42: B
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $43: C
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $44: D
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $45: E
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $46: F
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $47: G
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $48: H
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $49: I
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4A: J
|
||||
db %00111110
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %01001100
|
||||
db %01111100
|
||||
db %00111000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4B: K
|
||||
db %01100110
|
||||
db %01101100
|
||||
db %01111000
|
||||
db %01111000
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4C: L
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4D: M
|
||||
db %01000010
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4E: N
|
||||
db %01000110
|
||||
db %01100110
|
||||
db %01110110
|
||||
db %01111110
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4F: O
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $50: P
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $51: Q
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100010
|
||||
db %01101010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $52: R
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $53: S
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $54: T
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $55: U
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $56: V
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00100100
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $57: W
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $58: X
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $59: Y
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5A: Z
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $5B: Opening square bracket "["
|
||||
db %00011100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011100
|
||||
|
||||
// $5C: Back slash "\"
|
||||
db %01000000
|
||||
db %01100000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00000110
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $5D: Closing square bracket "]"
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111000
|
||||
|
||||
// $5E: Caret "^"
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5F: Underscore "_"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %11111111
|
||||
|
||||
// $60: Opening single quote "`"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $61: a
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01100100
|
||||
db %01100100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $62: b
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00111100
|
||||
db %00110010
|
||||
db %00110010
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $63: c
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $64: d
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $65: e
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01101000
|
||||
db %01110010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $66: f
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011100
|
||||
db %00110010
|
||||
db %00110000
|
||||
db %01111100
|
||||
db %00110000
|
||||
db %00110000
|
||||
|
||||
// $67: g
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111010
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $68: h
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $69: i
|
||||
db %00110000
|
||||
db %00000000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6A: j
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $6B: k
|
||||
db %01100000
|
||||
db %01100100
|
||||
db %01101000
|
||||
db %01111000
|
||||
db %01100100
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6C: l
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6D: m
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01010100
|
||||
db %01101010
|
||||
db %01101010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6E: n
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6F: o
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $70: p
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
|
||||
// $71: q
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00110100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111100
|
||||
db %00001110
|
||||
db %00001100
|
||||
|
||||
// $72: r
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $73: s
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %00011000
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $74: t
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %01111000
|
||||
db %00110000
|
||||
db %00110010
|
||||
db %00011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $75: u
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $76: v
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $77: w
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %00101100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $78: x
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $79: y
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $7A: z
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $7B: Opening curly bracket "{"
|
||||
db %00011100
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011100
|
||||
|
||||
// $7C: Vertical line "|"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
|
||||
// $7D: Closing curly bracket "{"
|
||||
db %00111000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111000
|
||||
|
||||
// $7E: Tilde "~"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01110000
|
||||
db %01011010
|
||||
db %00001110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
507
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/LIB/SNES.INC
Normal file
507
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/LIB/SNES.INC
Normal file
@ -0,0 +1,507 @@
|
||||
//============== (Key: R=Read, W=Write, D=Double Read/Write)
|
||||
// SNES Include
|
||||
//==============
|
||||
// Memory Map
|
||||
constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW
|
||||
|
||||
// PPU Picture Processing Unit Ports (Write-Only)
|
||||
constant REG_INIDISP($2100) // Display Control 1 1B/W
|
||||
constant REG_OBSEL($2101) // Object Size & Object Base 1B/W
|
||||
constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W
|
||||
constant REG_OAMDATA($2104) // OAM Data Write 1B/W D
|
||||
constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W
|
||||
constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W
|
||||
constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W
|
||||
constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W
|
||||
constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D
|
||||
constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D
|
||||
constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W
|
||||
constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W
|
||||
constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W
|
||||
constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W
|
||||
constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W
|
||||
constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D
|
||||
constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D
|
||||
constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D
|
||||
constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D
|
||||
constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D
|
||||
constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D
|
||||
constant REG_CGADD($2121) // Palette CGRAM Address 1B/W
|
||||
constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D
|
||||
constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W
|
||||
constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W
|
||||
constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W
|
||||
constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W
|
||||
constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W
|
||||
constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W
|
||||
constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W
|
||||
constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W
|
||||
constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W
|
||||
constant REG_TM($212C) // Main Screen Designation 1B/W
|
||||
constant REG_TS($212D) // Sub Screen Designation 1B/W
|
||||
constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W
|
||||
constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W
|
||||
constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W
|
||||
constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W
|
||||
constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W
|
||||
constant REG_SETINI($2133) // Display Control 2 1B/W
|
||||
|
||||
// PPU Picture Processing Unit Ports (Read-Only)
|
||||
constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R
|
||||
constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R
|
||||
constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R
|
||||
constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R
|
||||
constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D
|
||||
constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R
|
||||
constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R
|
||||
constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D
|
||||
constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D
|
||||
constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D
|
||||
constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R
|
||||
constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R
|
||||
|
||||
// APU Audio Processing Unit Ports (Read/Write)
|
||||
constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW
|
||||
constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW
|
||||
constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW
|
||||
constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW
|
||||
// $2140..$2143 - APU Ports Mirrored To $2144..$217F
|
||||
|
||||
// WRAM Access Ports
|
||||
constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW
|
||||
constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W
|
||||
constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W
|
||||
constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W
|
||||
// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus)
|
||||
// $2200..$3FFF - Unused Region (A-Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz)
|
||||
// ($4000..$4015 - Unused Region (Open Bus)
|
||||
constant REG_JOYWR($4016) // Joypad Output 1B/W
|
||||
constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R
|
||||
constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R
|
||||
// $4018..$41FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Write-only, Read=Open Bus)
|
||||
constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W
|
||||
constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W
|
||||
constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W
|
||||
constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W
|
||||
constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W
|
||||
constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W
|
||||
constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W
|
||||
constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W
|
||||
constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W
|
||||
constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W
|
||||
constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W
|
||||
constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W
|
||||
// $420E..$420F - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Read-only)
|
||||
constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R
|
||||
constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R
|
||||
constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R
|
||||
constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R
|
||||
constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R
|
||||
constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R
|
||||
constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R
|
||||
constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R
|
||||
// $4220..$42FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port)
|
||||
constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW
|
||||
// $430C..$430E - Unused Region (Open Bus)
|
||||
constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW
|
||||
|
||||
constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW
|
||||
// $431C..$431E - Unused Region (Open Bus)
|
||||
constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW
|
||||
|
||||
constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW
|
||||
// $432C..$432E - Unused Region (Open Bus)
|
||||
constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW
|
||||
|
||||
constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW
|
||||
// $433C..$433E - Unused Region (Open Bus)
|
||||
constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW
|
||||
|
||||
constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW
|
||||
// $434C..$434E - Unused Region (Open Bus)
|
||||
constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW
|
||||
|
||||
constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW
|
||||
// $435C..$435E - Unused Region (Open Bus)
|
||||
constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW
|
||||
|
||||
constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW
|
||||
// $436C..$436E - Unused Region (Open Bus)
|
||||
constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW
|
||||
|
||||
constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW
|
||||
// $437C..$437E - Unused Region (Open Bus)
|
||||
constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW
|
||||
// $4380..$5FFF - Unused Region (Open Bus)
|
||||
|
||||
// Further Memory
|
||||
// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges)
|
||||
// $8000..$FFFF - Cartridge ROM
|
||||
|
||||
//================================================
|
||||
// ReadD16 - Read Double 8-bit To Memory (16-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro ReadD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} // Load Source High Byte
|
||||
sta {DEST} + 1 // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// ReadD16Index - Read Double 8-bit To Index (16-Bit)
|
||||
//====================================================
|
||||
// SRC: Source Address
|
||||
// REG: Destination Index Register (x, y)
|
||||
macro ReadD16Index(SRC, REG) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
lda {SRC} // Load Source High Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
ta{REG} // Transfer 16-Bit A To 16-Bit REG
|
||||
}
|
||||
|
||||
//================================================
|
||||
// WriteD8 - Write Memory To Double 8-bit (8-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD8(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//==================================================
|
||||
// WriteD16 - Write Memory To Double 8-bit (16-Bit)
|
||||
//==================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} + 1 // Load Source High Byte
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// WriteD8Index - Write Index To Double 8-bit (8-Bit)
|
||||
//====================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD8Index(REG, DEST) {
|
||||
t{REG}a // Transfer 8-Bit REG To 8-Bit A
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//======================================================
|
||||
// WriteD16Index - Write Index To Double 8-bit (16-Bit)
|
||||
//======================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD16Index(REG, DEST) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Transfer 16-Bit REG To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//=====================
|
||||
// SNES Initialisation
|
||||
//=====================
|
||||
// ROMSPEED: ROM Speed (SLOWROM, FASTROM)
|
||||
constant SLOWROM(0) // Access Cycle Designation (Slow ROM)
|
||||
constant FASTROM(1) // Access Cycle Designation (Fast ROM)
|
||||
macro SNES_INIT(ROMSPEED) {
|
||||
sei // Disable Interrupts
|
||||
clc // Clear Carry To Switch To Native Mode
|
||||
xce // Xchange Carry & Emulation Bit (Native Mode)
|
||||
|
||||
phk
|
||||
plb
|
||||
rep #$38
|
||||
|
||||
ldx.w #$1FFF // Set Stack To $1FFF
|
||||
txs // Transfer Index Register X To Stack Pointer
|
||||
|
||||
lda.w #$0000
|
||||
tcd
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
|
||||
lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1
|
||||
sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM)
|
||||
|
||||
lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness)
|
||||
sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100)
|
||||
|
||||
stz.w REG_OBSEL // Object Size & Object Base ($2101)
|
||||
stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102)
|
||||
stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103)
|
||||
stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105)
|
||||
stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106)
|
||||
stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107)
|
||||
stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108)
|
||||
stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109)
|
||||
stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A)
|
||||
stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B)
|
||||
stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114)
|
||||
|
||||
lda.b #$01
|
||||
stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B)
|
||||
sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D)
|
||||
stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E)
|
||||
sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120)
|
||||
|
||||
stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123)
|
||||
stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124)
|
||||
stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125)
|
||||
stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126)
|
||||
stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127)
|
||||
stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128)
|
||||
stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129)
|
||||
stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A)
|
||||
stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B)
|
||||
stz.w REG_TM // Main Screen Designation = 0 ($212C)
|
||||
stz.w REG_TS // Sub Screen Designation = 0 ($212D)
|
||||
stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E)
|
||||
stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F)
|
||||
|
||||
lda.b #$30
|
||||
sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130)
|
||||
stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131)
|
||||
|
||||
lda.b #$E0
|
||||
sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132)
|
||||
stz.w REG_SETINI // Display Control 2 = 0 ($2133)
|
||||
|
||||
stz.w REG_JOYWR // Joypad Output = 0 ($4016)
|
||||
|
||||
stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200)
|
||||
|
||||
lda.b #$FF
|
||||
sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201)
|
||||
|
||||
stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202)
|
||||
stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203)
|
||||
stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204)
|
||||
stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205)
|
||||
stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206)
|
||||
stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207)
|
||||
stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208)
|
||||
stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209)
|
||||
stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A)
|
||||
stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B)
|
||||
stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C)
|
||||
|
||||
// Clear OAM
|
||||
ldx.w #$0080
|
||||
lda.b #$E0
|
||||
-
|
||||
sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104)
|
||||
sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
ldx.w #$0020
|
||||
-
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
// Clear WRAM
|
||||
ldy.w #$0000
|
||||
sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181)
|
||||
stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183)
|
||||
|
||||
ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom
|
||||
lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank)
|
||||
stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302)
|
||||
sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
nop // Delay
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B)
|
||||
|
||||
// VRAM
|
||||
lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119)
|
||||
sta.w REG_VMAIN // VRAM Address Increment Mode ($2115)
|
||||
ldy.w #$0000
|
||||
sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
// CGRAM
|
||||
stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121)
|
||||
ldx.w #$200 // 512 Byte
|
||||
stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305)
|
||||
ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
jml +
|
||||
|
||||
CONST_ZERO:
|
||||
dw $0000
|
||||
|
||||
+
|
||||
}
|
||||
558
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/LIB/SNES_GFX.INC
Normal file
558
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/LIB/SNES_GFX.INC
Normal file
@ -0,0 +1,558 @@
|
||||
//===============
|
||||
// SNES Graphics
|
||||
//===============
|
||||
|
||||
//=============================
|
||||
// WaitNMI - Wait For NMI Flag
|
||||
//=============================
|
||||
macro WaitNMI() {
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
}
|
||||
|
||||
//======================================
|
||||
// WaitHV - Wait For H/V Timer IRQ Flag
|
||||
//======================================
|
||||
macro WaitHV() {
|
||||
-
|
||||
bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag
|
||||
bpl - // Wait For H/V Timer IRQ Flag
|
||||
}
|
||||
|
||||
//========================================
|
||||
// WaitHVB - Wait For V-Blank Period Flag
|
||||
//========================================
|
||||
macro WaitHVB() {
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
}
|
||||
|
||||
//================================================================
|
||||
// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing)
|
||||
//================================================================
|
||||
macro FadeIN() {
|
||||
ldx.w #$0000 // Set X To Mininmum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
inx // Increments Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$0F // Compare With Maximum Brightness Level (15)
|
||||
bne - // IF (Screen != Maximum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//=================================================================
|
||||
// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing)
|
||||
//=================================================================
|
||||
macro FadeOUT() {
|
||||
ldx.w #$000F // Set X To Maximum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
dex // Decrement Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$00 // Compare With Minimum Brightness Level
|
||||
bne - // IF (Screen != Minimum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//======================================
|
||||
// LoadPAL - Load Palette Data To CGRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadPAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==========================================
|
||||
// UpdatePAL - Update Palette Data To CGRAM
|
||||
//==========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdatePAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearLOVRAM - Clear VRAM Lo Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearHIVRAM - Clear VRAM Hi Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===================================
|
||||
// ClearVRAM - Clear VRAM Fixed Word
|
||||
//===================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
// Transfer Lo Byte
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Transfer Hi Byte
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==================================
|
||||
// LoadVRAM - Load GFX Data To VRAM
|
||||
//==================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================================
|
||||
// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride
|
||||
//========================================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// STRIDE: Dest Offset Stride
|
||||
// COUNT: Number Of DMA Transfers
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
-
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
txa // A = X
|
||||
clc // Clear Carry Flag
|
||||
adc.w #{STRIDE} >> 1
|
||||
tax // X = A
|
||||
lda.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1
|
||||
bne -
|
||||
}
|
||||
|
||||
//======================================
|
||||
// UpdateVRAM - Update GFX Data To VRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdateVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===========================================
|
||||
// LoadM7VRAM - Load Mode 7 GFX Data To VRAM
|
||||
//===========================================
|
||||
// SRCMAP: 24-Bit Address Of Source Map Data
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZEMAP: Size Of Map Data (BYTE Size)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) {
|
||||
// Load Mode7 Map Data To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCMAP} // Set Source Offset (Map)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCMAP} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map)
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset (Tiles)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8 - Scroll GFX BG From Memory (8-Bit)
|
||||
//===============================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8(BGSCR, BGPOS, DIR) {
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16 - Scroll GFX BG From Memory (16-Bit)
|
||||
//=================================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16(BGSCR, BGPOS, DIR) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
lda {BGSCR} + 1 // Load BG Scroll Position High Byte
|
||||
sta {BGPOS} // Store BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8I - Scroll GFX BG From Index (8-Bit)
|
||||
//===============================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
t{REG}a // Swaps 8-Bit Index To 8-Bit A
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16I - Scroll GFX BG From Index (16-Bit)
|
||||
//=================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Word
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Swaps 16-Bit Index To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {BGPOS} // Store A To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//======================================
|
||||
// Mode7CALC - Mode7 Matrix Calculation
|
||||
//======================================
|
||||
// A: Mode7 COS A Word
|
||||
// B: Mode7 SIN A Word
|
||||
// C: Mode7 SIN B Word
|
||||
// D: Mode7 COS B Word
|
||||
// ANGLE: Mode7 Angle Byte
|
||||
// SX: Mode7 Scale X Word
|
||||
// SY: Mode7 Scale Y Word
|
||||
// SINCOS: Mode7 SINCOS Table
|
||||
macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) {
|
||||
lda.b {ANGLE} // Load Angle To A
|
||||
tax // Transfer A To X
|
||||
|
||||
// Calculate B & C (SIN)
|
||||
// B
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {B}
|
||||
// C
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1 // High Byte
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
eor.b #$FF // Make Negative
|
||||
inc
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {C}
|
||||
|
||||
// Change X Index To Point To COS Values (X + 64)
|
||||
txa // Transfer X Index To A
|
||||
clc // Clear Carry Flag
|
||||
adc.b #64 // Add 64 With Carry
|
||||
tax // Transfer A To X Index
|
||||
|
||||
// Calculate A & D (COS)
|
||||
// A
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {A}
|
||||
// D
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {D}
|
||||
|
||||
// Store Result To Matrix
|
||||
lda.b {A}
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {A} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
|
||||
lda.b {B}
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
lda.b {B} + 1
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
|
||||
lda.b {C}
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
lda.b {C} + 1
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
|
||||
lda.b {D}
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
lda.b {D} + 1
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
//=============
|
||||
// SNES Header
|
||||
//=============
|
||||
seek($FFC0)
|
||||
// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes)
|
||||
db "65816 CPU TEST EOR "
|
||||
// "123456789012345678901"
|
||||
|
||||
// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode)
|
||||
db $20
|
||||
// ||___________________Map Mode:
|
||||
// | $X0 = LoROM/32K Banks (Mode 20)
|
||||
// | $X1 = HiROM/64K Banks (Mode 21)
|
||||
// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable)
|
||||
// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable)
|
||||
// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM)
|
||||
// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable)
|
||||
|
||||
// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type)
|
||||
db $00
|
||||
// ||___________________Type:
|
||||
// | $00 = ROM
|
||||
// | $01 = ROM+RAM
|
||||
// Co-processor: $02 = ROM+RAM+Battery
|
||||
// $0X = DSP $X3 = ROM+Co-processor
|
||||
// $1X = GSU $X4 = ROM+Co-processor+RAM
|
||||
// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery
|
||||
// $3X = SA-1 $X6 = ROM+Co-processor+Battery
|
||||
// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513
|
||||
// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked
|
||||
|
||||
// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits)
|
||||
db $01
|
||||
// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit)
|
||||
// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit)
|
||||
// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit)
|
||||
// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit)
|
||||
// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit)
|
||||
// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit)
|
||||
|
||||
// RAM SIZE
|
||||
db $00
|
||||
// $00 = None, $04 = 16Kb
|
||||
// $01 = 2Kb, $05 = 32Kb
|
||||
// $02 = 4Kb, $06 = 64Kb
|
||||
// $03 = 8Kb, $07 = 128Kb
|
||||
|
||||
// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz)
|
||||
db $00
|
||||
// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL)
|
||||
// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL)
|
||||
// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL)
|
||||
// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL)
|
||||
// $04 = Finland (PAL), $0D = South (K)orea (NTSC)
|
||||
// $05 = Denmark (PAL), $0E = (A)Common (ANY)
|
||||
// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC)
|
||||
// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M)
|
||||
// $08 = (S)pain (PAL), $11 = (U)Australia (PAL)
|
||||
|
||||
// DEVELOPER ID CODE
|
||||
db $00
|
||||
// $00 = None
|
||||
// $01 = Nintendo
|
||||
// $33 = New (Uses Extended Header)
|
||||
|
||||
// ROM VERSION NUMBER
|
||||
db $00
|
||||
// $00 = 1.00, $01 = 1.01
|
||||
|
||||
// COMPLEMENT CHECK
|
||||
db "CC"
|
||||
// CHECKSUM
|
||||
db "CS"
|
||||
|
||||
// NATIVE VECTOR (65C816 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (BRK Opcode)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $0000 // RESET VECTOR (Unused)
|
||||
dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt)
|
||||
|
||||
// EMU VECTOR (6502 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (Unused)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET)
|
||||
dw $0000 // IRQ/BRK VECTOR
|
||||
1
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/make.bat
Normal file
1
OSBindings/Mac/Clock SignalTests/krom 65816/EOR/make.bat
Normal file
@ -0,0 +1 @@
|
||||
bass CPUEOR.asm
|
||||
1334
OSBindings/Mac/Clock SignalTests/krom 65816/INC/CPUINC.asm
Normal file
1334
OSBindings/Mac/Clock SignalTests/krom 65816/INC/CPUINC.asm
Normal file
File diff suppressed because it is too large
Load Diff
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/INC/CPUINC.png
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/INC/CPUINC.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.3 KiB |
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/INC/CPUINC.sfc
Normal file
BIN
OSBindings/Mac/Clock SignalTests/krom 65816/INC/CPUINC.sfc
Normal file
Binary file not shown.
957
OSBindings/Mac/Clock SignalTests/krom 65816/INC/Font8x8.asm
Normal file
957
OSBindings/Mac/Clock SignalTests/krom 65816/INC/Font8x8.asm
Normal file
@ -0,0 +1,957 @@
|
||||
fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes
|
||||
|
||||
// $20: Space " "
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $21: Exclamation mark "!"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $22: Quotation mark """
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $23: Cross hatch "#"
|
||||
db %00010100
|
||||
db %00010100
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %01111110
|
||||
db %00101000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $24: Dollar sign "$"
|
||||
db %00111100
|
||||
db %01101010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01010110
|
||||
db %00111100
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $25: Percent sign "%"
|
||||
db %00100010
|
||||
db %01010100
|
||||
db %00101000
|
||||
db %00010100
|
||||
db %00101010
|
||||
db %01000100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $26: Ampersand "&"
|
||||
db %00110000
|
||||
db %01001000
|
||||
db %00110010
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00110010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $27: Closing single quote "'"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $28: Opening parentheses "("
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
|
||||
// $29: Closing parentheses ")"
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
|
||||
// $2A: Asterisk "*"
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2B: Plus "+"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2C: Comma ","
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $2D: Hyphen "-"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2E: Period "."
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $2F: Forward slash "/"
|
||||
db %00000010
|
||||
db %00000110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01100000
|
||||
db %01000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $30: 0
|
||||
db %00111010
|
||||
db %01100100
|
||||
db %01001010
|
||||
db %01010010
|
||||
db %00100110
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $31: 1
|
||||
db %00011000
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $32: 2
|
||||
db %00111000
|
||||
db %01001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $33: 3
|
||||
db %00111100
|
||||
db %01000110
|
||||
db %00011100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $34: 4
|
||||
db %00001100
|
||||
db %00011100
|
||||
db %00101100
|
||||
db %01001100
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $35: 5
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $36: 6
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $37: 7
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $38: 8
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $39: 9
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %00000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $3A: Colon ":"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3B: Semicolon ";"
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00010000
|
||||
db %00000000
|
||||
|
||||
// $3C: Less than sign "<"
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3D: Equals sign "="
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3E: Greater than sign ">"
|
||||
db %00000000
|
||||
db %01100000
|
||||
db %00011000
|
||||
db %00000110
|
||||
db %00011000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $3F: Question mark "?"
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00011000
|
||||
db %00000000
|
||||
|
||||
// $40: At sign "@"
|
||||
db %01111100
|
||||
db %10000010
|
||||
db %10111010
|
||||
db %10101010
|
||||
db %10111110
|
||||
db %01000000
|
||||
db %00111110
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $41: A
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %00100100
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $42: B
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $43: C
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $44: D
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $45: E
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $46: F
|
||||
db %01111110
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $47: G
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100000
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $48: H
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $49: I
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4A: J
|
||||
db %00111110
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %01001100
|
||||
db %01111100
|
||||
db %00111000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4B: K
|
||||
db %01100110
|
||||
db %01101100
|
||||
db %01111000
|
||||
db %01111000
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4C: L
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4D: M
|
||||
db %01000010
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4E: N
|
||||
db %01000110
|
||||
db %01100110
|
||||
db %01110110
|
||||
db %01111110
|
||||
db %01101110
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $4F: O
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $50: P
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $51: Q
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01100010
|
||||
db %01101010
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $52: R
|
||||
db %01111100
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %01111100
|
||||
db %01101100
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $53: S
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01111100
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $54: T
|
||||
db %01111110
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $55: U
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $56: V
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00100100
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $57: W
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %01111110
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $58: X
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00111100
|
||||
db %01100110
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $59: Y
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5A: Z
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $5B: Opening square bracket "["
|
||||
db %00011100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011100
|
||||
|
||||
// $5C: Back slash "\"
|
||||
db %01000000
|
||||
db %01100000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00000110
|
||||
db %00000010
|
||||
db %00000000
|
||||
|
||||
// $5D: Closing square bracket "]"
|
||||
db %00111000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00111000
|
||||
|
||||
// $5E: Caret "^"
|
||||
db %00011000
|
||||
db %00100100
|
||||
db %01000010
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $5F: Underscore "_"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %11111111
|
||||
|
||||
// $60: Opening single quote "`"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $61: a
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01100100
|
||||
db %01100100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $62: b
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00111100
|
||||
db %00110010
|
||||
db %00110010
|
||||
db %01011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $63: c
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100000
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $64: d
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $65: e
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111000
|
||||
db %01101000
|
||||
db %01110010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $66: f
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00011100
|
||||
db %00110010
|
||||
db %00110000
|
||||
db %01111100
|
||||
db %00110000
|
||||
db %00110000
|
||||
|
||||
// $67: g
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111010
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $68: h
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %01111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $69: i
|
||||
db %00110000
|
||||
db %00000000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6A: j
|
||||
db %00000110
|
||||
db %00000000
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %00000110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $6B: k
|
||||
db %01100000
|
||||
db %01100100
|
||||
db %01101000
|
||||
db %01111000
|
||||
db %01100100
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6C: l
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6D: m
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01010100
|
||||
db %01101010
|
||||
db %01101010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6E: n
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $6F: o
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $70: p
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01111100
|
||||
db %01100000
|
||||
db %01100000
|
||||
|
||||
// $71: q
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00110100
|
||||
db %01001100
|
||||
db %01001100
|
||||
db %00111100
|
||||
db %00001110
|
||||
db %00001100
|
||||
|
||||
// $72: r
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01011100
|
||||
db %01100010
|
||||
db %01100000
|
||||
db %01100000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $73: s
|
||||
db %00000000
|
||||
db %00111100
|
||||
db %01100010
|
||||
db %00011000
|
||||
db %01000110
|
||||
db %00111100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $74: t
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %01111000
|
||||
db %00110000
|
||||
db %00110010
|
||||
db %00011100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $75: u
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111010
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $76: v
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $77: w
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01000010
|
||||
db %01011010
|
||||
db %01011010
|
||||
db %00101100
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $78: x
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100010
|
||||
db %00110100
|
||||
db %00011000
|
||||
db %01100110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
// $79: y
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %01100110
|
||||
db %00111110
|
||||
db %01000110
|
||||
db %00111100
|
||||
|
||||
// $7A: z
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01111110
|
||||
db %00001100
|
||||
db %00110000
|
||||
db %01111110
|
||||
db %00000000
|
||||
db %00000000
|
||||
|
||||
//////////////////////////////////////////
|
||||
// $7B: Opening curly bracket "{"
|
||||
db %00011100
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00110000
|
||||
db %00110000
|
||||
db %00011100
|
||||
|
||||
// $7C: Vertical line "|"
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00011000
|
||||
|
||||
// $7D: Closing curly bracket "{"
|
||||
db %00111000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00011000
|
||||
db %00011000
|
||||
db %00001100
|
||||
db %00001100
|
||||
db %00111000
|
||||
|
||||
// $7E: Tilde "~"
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %01110000
|
||||
db %01011010
|
||||
db %00001110
|
||||
db %00000000
|
||||
db %00000000
|
||||
db %00000000
|
||||
507
OSBindings/Mac/Clock SignalTests/krom 65816/INC/LIB/SNES.INC
Normal file
507
OSBindings/Mac/Clock SignalTests/krom 65816/INC/LIB/SNES.INC
Normal file
@ -0,0 +1,507 @@
|
||||
//============== (Key: R=Read, W=Write, D=Double Read/Write)
|
||||
// SNES Include
|
||||
//==============
|
||||
// Memory Map
|
||||
constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW
|
||||
|
||||
// PPU Picture Processing Unit Ports (Write-Only)
|
||||
constant REG_INIDISP($2100) // Display Control 1 1B/W
|
||||
constant REG_OBSEL($2101) // Object Size & Object Base 1B/W
|
||||
constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W
|
||||
constant REG_OAMDATA($2104) // OAM Data Write 1B/W D
|
||||
constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W
|
||||
constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W
|
||||
constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W
|
||||
constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W
|
||||
constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W
|
||||
constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D
|
||||
constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D
|
||||
constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D
|
||||
constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D
|
||||
constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W
|
||||
constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W
|
||||
constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W
|
||||
constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W
|
||||
constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W
|
||||
constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W
|
||||
constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D
|
||||
constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D
|
||||
constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D
|
||||
constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D
|
||||
constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D
|
||||
constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D
|
||||
constant REG_CGADD($2121) // Palette CGRAM Address 1B/W
|
||||
constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D
|
||||
constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W
|
||||
constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W
|
||||
constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W
|
||||
constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W
|
||||
constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W
|
||||
constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W
|
||||
constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W
|
||||
constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W
|
||||
constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W
|
||||
constant REG_TM($212C) // Main Screen Designation 1B/W
|
||||
constant REG_TS($212D) // Sub Screen Designation 1B/W
|
||||
constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W
|
||||
constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W
|
||||
constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W
|
||||
constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W
|
||||
constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W
|
||||
constant REG_SETINI($2133) // Display Control 2 1B/W
|
||||
|
||||
// PPU Picture Processing Unit Ports (Read-Only)
|
||||
constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R
|
||||
constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R
|
||||
constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R
|
||||
constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R
|
||||
constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D
|
||||
constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R
|
||||
constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R
|
||||
constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D
|
||||
constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D
|
||||
constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D
|
||||
constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R
|
||||
constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R
|
||||
|
||||
// APU Audio Processing Unit Ports (Read/Write)
|
||||
constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW
|
||||
constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW
|
||||
constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW
|
||||
constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW
|
||||
// $2140..$2143 - APU Ports Mirrored To $2144..$217F
|
||||
|
||||
// WRAM Access Ports
|
||||
constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW
|
||||
constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W
|
||||
constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W
|
||||
constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W
|
||||
// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus)
|
||||
// $2200..$3FFF - Unused Region (A-Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz)
|
||||
// ($4000..$4015 - Unused Region (Open Bus)
|
||||
constant REG_JOYWR($4016) // Joypad Output 1B/W
|
||||
constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R
|
||||
constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R
|
||||
// $4018..$41FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Write-only, Read=Open Bus)
|
||||
constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W
|
||||
constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W
|
||||
constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W
|
||||
constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W
|
||||
constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W
|
||||
constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W
|
||||
constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W
|
||||
constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W
|
||||
constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W
|
||||
constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W
|
||||
constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W
|
||||
constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W
|
||||
constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W
|
||||
// $420E..$420F - Unused Region (Open Bus)
|
||||
|
||||
// CPU On-Chip I/O Ports (Read-only)
|
||||
constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R
|
||||
constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R
|
||||
constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R
|
||||
constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R
|
||||
constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R
|
||||
constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R
|
||||
constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R
|
||||
constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R
|
||||
constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R
|
||||
constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R
|
||||
// $4220..$42FF - Unused Region (Open Bus)
|
||||
|
||||
// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port)
|
||||
constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW
|
||||
// $430C..$430E - Unused Region (Open Bus)
|
||||
constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW
|
||||
|
||||
constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW
|
||||
// $431C..$431E - Unused Region (Open Bus)
|
||||
constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW
|
||||
|
||||
constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW
|
||||
// $432C..$432E - Unused Region (Open Bus)
|
||||
constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW
|
||||
|
||||
constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW
|
||||
// $433C..$433E - Unused Region (Open Bus)
|
||||
constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW
|
||||
|
||||
constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW
|
||||
// $434C..$434E - Unused Region (Open Bus)
|
||||
constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW
|
||||
|
||||
constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW
|
||||
// $435C..$435E - Unused Region (Open Bus)
|
||||
constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW
|
||||
|
||||
constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW
|
||||
// $436C..$436E - Unused Region (Open Bus)
|
||||
constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW
|
||||
|
||||
constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW
|
||||
constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW
|
||||
constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW
|
||||
constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW
|
||||
constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW
|
||||
constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW
|
||||
constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW
|
||||
constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW
|
||||
// $437C..$437E - Unused Region (Open Bus)
|
||||
constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW
|
||||
// $4380..$5FFF - Unused Region (Open Bus)
|
||||
|
||||
// Further Memory
|
||||
// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges)
|
||||
// $8000..$FFFF - Cartridge ROM
|
||||
|
||||
//================================================
|
||||
// ReadD16 - Read Double 8-bit To Memory (16-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro ReadD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} // Load Source High Byte
|
||||
sta {DEST} + 1 // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// ReadD16Index - Read Double 8-bit To Index (16-Bit)
|
||||
//====================================================
|
||||
// SRC: Source Address
|
||||
// REG: Destination Index Register (x, y)
|
||||
macro ReadD16Index(SRC, REG) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
lda {SRC} // Load Source High Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
ta{REG} // Transfer 16-Bit A To 16-Bit REG
|
||||
}
|
||||
|
||||
//================================================
|
||||
// WriteD8 - Write Memory To Double 8-bit (8-Bit)
|
||||
//================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD8(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//==================================================
|
||||
// WriteD16 - Write Memory To Double 8-bit (16-Bit)
|
||||
//==================================================
|
||||
// SRC: Source Address
|
||||
// DEST: Destination Address
|
||||
macro WriteD16(SRC, DEST) {
|
||||
lda {SRC} // Load Source Low Byte
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
lda {SRC} + 1 // Load Source High Byte
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//====================================================
|
||||
// WriteD8Index - Write Index To Double 8-bit (8-Bit)
|
||||
//====================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD8Index(REG, DEST) {
|
||||
t{REG}a // Transfer 8-Bit REG To 8-Bit A
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
stz {DEST} // Store Zero To Destination High Byte
|
||||
}
|
||||
|
||||
//======================================================
|
||||
// WriteD16Index - Write Index To Double 8-bit (16-Bit)
|
||||
//======================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// DEST: Destination Address
|
||||
macro WriteD16Index(REG, DEST) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Transfer 16-Bit REG To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {DEST} // Store Destination Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {DEST} // Store Destination High Byte
|
||||
}
|
||||
|
||||
//=====================
|
||||
// SNES Initialisation
|
||||
//=====================
|
||||
// ROMSPEED: ROM Speed (SLOWROM, FASTROM)
|
||||
constant SLOWROM(0) // Access Cycle Designation (Slow ROM)
|
||||
constant FASTROM(1) // Access Cycle Designation (Fast ROM)
|
||||
macro SNES_INIT(ROMSPEED) {
|
||||
sei // Disable Interrupts
|
||||
clc // Clear Carry To Switch To Native Mode
|
||||
xce // Xchange Carry & Emulation Bit (Native Mode)
|
||||
|
||||
phk
|
||||
plb
|
||||
rep #$38
|
||||
|
||||
ldx.w #$1FFF // Set Stack To $1FFF
|
||||
txs // Transfer Index Register X To Stack Pointer
|
||||
|
||||
lda.w #$0000
|
||||
tcd
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
|
||||
lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1
|
||||
sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM)
|
||||
|
||||
lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness)
|
||||
sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100)
|
||||
|
||||
stz.w REG_OBSEL // Object Size & Object Base ($2101)
|
||||
stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102)
|
||||
stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103)
|
||||
stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105)
|
||||
stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106)
|
||||
stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107)
|
||||
stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108)
|
||||
stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109)
|
||||
stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A)
|
||||
stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B)
|
||||
stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D)
|
||||
stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E)
|
||||
stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F)
|
||||
stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110)
|
||||
stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111)
|
||||
stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112)
|
||||
stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113)
|
||||
stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114)
|
||||
stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114)
|
||||
|
||||
lda.b #$01
|
||||
stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B)
|
||||
sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C)
|
||||
stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D)
|
||||
stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D)
|
||||
stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E)
|
||||
sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F)
|
||||
stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120)
|
||||
stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120)
|
||||
|
||||
stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123)
|
||||
stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124)
|
||||
stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125)
|
||||
stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126)
|
||||
stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127)
|
||||
stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128)
|
||||
stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129)
|
||||
stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A)
|
||||
stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B)
|
||||
stz.w REG_TM // Main Screen Designation = 0 ($212C)
|
||||
stz.w REG_TS // Sub Screen Designation = 0 ($212D)
|
||||
stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E)
|
||||
stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F)
|
||||
|
||||
lda.b #$30
|
||||
sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130)
|
||||
stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131)
|
||||
|
||||
lda.b #$E0
|
||||
sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132)
|
||||
stz.w REG_SETINI // Display Control 2 = 0 ($2133)
|
||||
|
||||
stz.w REG_JOYWR // Joypad Output = 0 ($4016)
|
||||
|
||||
stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200)
|
||||
|
||||
lda.b #$FF
|
||||
sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201)
|
||||
|
||||
stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202)
|
||||
stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203)
|
||||
stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204)
|
||||
stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205)
|
||||
stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206)
|
||||
stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207)
|
||||
stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208)
|
||||
stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209)
|
||||
stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A)
|
||||
stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B)
|
||||
stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C)
|
||||
|
||||
// Clear OAM
|
||||
ldx.w #$0080
|
||||
lda.b #$E0
|
||||
-
|
||||
sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104)
|
||||
sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104)
|
||||
stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
ldx.w #$0020
|
||||
-
|
||||
stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104)
|
||||
dex
|
||||
bne -
|
||||
|
||||
// Clear WRAM
|
||||
ldy.w #$0000
|
||||
sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181)
|
||||
stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183)
|
||||
|
||||
ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom
|
||||
lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank)
|
||||
stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302)
|
||||
sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
nop // Delay
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B)
|
||||
|
||||
// VRAM
|
||||
lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119)
|
||||
sta.w REG_VMAIN // VRAM Address Increment Mode ($2115)
|
||||
ldy.w #$0000
|
||||
sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116)
|
||||
sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305)
|
||||
|
||||
ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
|
||||
lda.b #$01
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
// CGRAM
|
||||
stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121)
|
||||
ldx.w #$200 // 512 Byte
|
||||
stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305)
|
||||
ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122)
|
||||
stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300)
|
||||
sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B)
|
||||
|
||||
jml +
|
||||
|
||||
CONST_ZERO:
|
||||
dw $0000
|
||||
|
||||
+
|
||||
}
|
||||
558
OSBindings/Mac/Clock SignalTests/krom 65816/INC/LIB/SNES_GFX.INC
Normal file
558
OSBindings/Mac/Clock SignalTests/krom 65816/INC/LIB/SNES_GFX.INC
Normal file
@ -0,0 +1,558 @@
|
||||
//===============
|
||||
// SNES Graphics
|
||||
//===============
|
||||
|
||||
//=============================
|
||||
// WaitNMI - Wait For NMI Flag
|
||||
//=============================
|
||||
macro WaitNMI() {
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
}
|
||||
|
||||
//======================================
|
||||
// WaitHV - Wait For H/V Timer IRQ Flag
|
||||
//======================================
|
||||
macro WaitHV() {
|
||||
-
|
||||
bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag
|
||||
bpl - // Wait For H/V Timer IRQ Flag
|
||||
}
|
||||
|
||||
//========================================
|
||||
// WaitHVB - Wait For V-Blank Period Flag
|
||||
//========================================
|
||||
macro WaitHVB() {
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
}
|
||||
|
||||
//================================================================
|
||||
// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing)
|
||||
//================================================================
|
||||
macro FadeIN() {
|
||||
ldx.w #$0000 // Set X To Mininmum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
inx // Increments Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$0F // Compare With Maximum Brightness Level (15)
|
||||
bne - // IF (Screen != Maximum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//=================================================================
|
||||
// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing)
|
||||
//=================================================================
|
||||
macro FadeOUT() {
|
||||
ldx.w #$000F // Set X To Maximum Brightness Level
|
||||
-
|
||||
bit.w REG_RDNMI // $4210: Read NMI Flag Register
|
||||
bpl - // Wait For NMI Flag
|
||||
|
||||
dex // Decrement Brightness Level
|
||||
txa // Swap 16-Bit X To 8-Bit A
|
||||
sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level
|
||||
cmp.b #$00 // Compare With Minimum Brightness Level
|
||||
bne - // IF (Screen != Minimum Brightness Level) Loop
|
||||
}
|
||||
|
||||
//======================================
|
||||
// LoadPAL - Load Palette Data To CGRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadPAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==========================================
|
||||
// UpdatePAL - Update Palette Data To CGRAM
|
||||
//==========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 9-Bit CGRAM Destination Address (Color # To Start On)
|
||||
// SIZE: Size Of Data (# Of Colors To Copy)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdatePAL(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #{DEST} // Set CGRAM Destination
|
||||
sta.w REG_CGADD // $2121: CGRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$22 // Set Destination Register ($2122: CGRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color)
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearLOVRAM - Clear VRAM Lo Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================
|
||||
// ClearHIVRAM - Clear VRAM Hi Fixed Byte
|
||||
//========================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===================================
|
||||
// ClearVRAM - Clear VRAM Fixed Word
|
||||
//===================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro ClearVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
// Transfer Lo Byte
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset (Lo Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Transfer Hi Byte
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//==================================
|
||||
// LoadVRAM - Load GFX Data To VRAM
|
||||
//==================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//========================================================
|
||||
// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride
|
||||
//========================================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// STRIDE: Dest Offset Stride
|
||||
// COUNT: Number Of DMA Transfers
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
-
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
rep #$20 // Set 16-Bit Accumulator
|
||||
txa // A = X
|
||||
clc // Clear Carry Flag
|
||||
adc.w #{STRIDE} >> 1
|
||||
tax // X = A
|
||||
lda.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1
|
||||
bne -
|
||||
}
|
||||
|
||||
//======================================
|
||||
// UpdateVRAM - Update GFX Data To VRAM
|
||||
//======================================
|
||||
// SRC: 24-Bit Address Of Source Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZE: Size Of Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro UpdateVRAM(SRC, DEST, SIZE, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$01 // Set DMA Mode (Write Word, Increment Source)
|
||||
sta.w REG_DMAP{CHAN} // $43X0: DMA Control
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRC} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRC} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
-
|
||||
bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag
|
||||
bpl - // Wait For V-Blank Period Flag
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===========================================
|
||||
// LoadM7VRAM - Load Mode 7 GFX Data To VRAM
|
||||
//===========================================
|
||||
// SRCMAP: 24-Bit Address Of Source Map Data
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZEMAP: Size Of Map Data (BYTE Size)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) {
|
||||
// Load Mode7 Map Data To VRAM
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCMAP} // Set Source Offset (Map)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCMAP} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
|
||||
// Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map)
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset (Tiles)
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control)
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$18 // Set Destination Register ($2118: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//=============================================
|
||||
// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes
|
||||
//=============================================
|
||||
// SRCTILES: 24-Bit Address Of Source Tile Data
|
||||
// DEST: 16-Bit VRAM Destination (WORD Address)
|
||||
// SIZETILES: Size Of Tile Data (BYTE Size)
|
||||
// CHAN: DMA Channel To Transfer Data (0..7)
|
||||
macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) {
|
||||
lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte
|
||||
sta.w REG_VMAIN // $2115: Video Port Control
|
||||
ldx.w #{DEST} >> 1 // Set VRAM Destination
|
||||
stx.w REG_VMADDL // $2116: VRAM
|
||||
|
||||
stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control)
|
||||
lda.b #$19 // Set Destination Register ($2119: VRAM Write)
|
||||
sta.w REG_BBAD{CHAN} // $43X1: DMA Destination
|
||||
ldx.w #{SRCTILES} // Set Source Offset
|
||||
stx.w REG_A1T{CHAN}L // $43X2: DMA Source
|
||||
lda.b #{SRCTILES} >> 16 // Set Source Bank
|
||||
sta.w REG_A1B{CHAN} // $43X4: Source Bank
|
||||
ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer
|
||||
stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA
|
||||
|
||||
lda.b #$01 << {CHAN} // Start DMA Transfer On Channel
|
||||
sta.w REG_MDMAEN // $420B: DMA Enable
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8 - Scroll GFX BG From Memory (8-Bit)
|
||||
//===============================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8(BGSCR, BGPOS, DIR) {
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16 - Scroll GFX BG From Memory (16-Bit)
|
||||
//=================================================
|
||||
// BGSCR: Source BG Scroll Position
|
||||
// BGPOS: Destination BG Pos Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16(BGSCR, BGPOS, DIR) {
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
{DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
lda {BGSCR} // Load BG Scroll Position Low Byte
|
||||
sta {BGPOS} // Store BG Scroll Position Low Byte
|
||||
lda {BGSCR} + 1 // Load BG Scroll Position High Byte
|
||||
sta {BGPOS} // Store BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//===============================================
|
||||
// BGScroll8I - Scroll GFX BG From Index (8-Bit)
|
||||
//===============================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll8I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte
|
||||
t{REG}a // Swaps 8-Bit Index To 8-Bit A
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
stz {BGPOS} // Store Zero To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//=================================================
|
||||
// BGScroll16I - Scroll GFX BG From Index (16-Bit)
|
||||
//=================================================
|
||||
// REG: Source Index Register (x, y)
|
||||
// BGPOS: Destination BG Position Register
|
||||
// DIR: Direction To Scroll (de = Decrement, in = Increment)
|
||||
macro BGScroll16I(REG, BGPOS, DIR) {
|
||||
{DIR}{REG} // Decrement Or Increment BG Scroll Position Word
|
||||
rep #$38 // Set 16-Bit Accumulator & Index
|
||||
t{REG}a // Swaps 16-Bit Index To 16-Bit A
|
||||
sep #$20 // Set 8-Bit Accumulator
|
||||
sta {BGPOS} // Store A To BG Scroll Position Low Byte
|
||||
xba // Exchange B & A Accumulators
|
||||
sta {BGPOS} // Store A To BG Scroll Position High Byte
|
||||
}
|
||||
|
||||
//======================================
|
||||
// Mode7CALC - Mode7 Matrix Calculation
|
||||
//======================================
|
||||
// A: Mode7 COS A Word
|
||||
// B: Mode7 SIN A Word
|
||||
// C: Mode7 SIN B Word
|
||||
// D: Mode7 COS B Word
|
||||
// ANGLE: Mode7 Angle Byte
|
||||
// SX: Mode7 Scale X Word
|
||||
// SY: Mode7 Scale Y Word
|
||||
// SINCOS: Mode7 SINCOS Table
|
||||
macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) {
|
||||
lda.b {ANGLE} // Load Angle To A
|
||||
tax // Transfer A To X
|
||||
|
||||
// Calculate B & C (SIN)
|
||||
// B
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {B}
|
||||
// C
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1 // High Byte
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // SIN(X)
|
||||
eor.b #$FF // Make Negative
|
||||
inc
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {C}
|
||||
|
||||
// Change X Index To Point To COS Values (X + 64)
|
||||
txa // Transfer X Index To A
|
||||
clc // Clear Carry Flag
|
||||
adc.b #64 // Add 64 With Carry
|
||||
tax // Transfer A To X Index
|
||||
|
||||
// Calculate A & D (COS)
|
||||
// A
|
||||
lda.b {SX} // Scale X
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SX} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {A}
|
||||
// D
|
||||
lda.b {SY} // Scale Y
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {SY} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.w {SINCOS},x // COS(X)
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8
|
||||
sty.w {D}
|
||||
|
||||
// Store Result To Matrix
|
||||
lda.b {A}
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
lda.b {A} + 1
|
||||
sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A)
|
||||
|
||||
lda.b {B}
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
lda.b {B} + 1
|
||||
sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B)
|
||||
|
||||
lda.b {C}
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
lda.b {C} + 1
|
||||
sta.w REG_M7C // $211D: MODE7 SINE B
|
||||
|
||||
lda.b {D}
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
lda.b {D} + 1
|
||||
sta.w REG_M7D // $211E: MODE7 COSINE B
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
//=============
|
||||
// SNES Header
|
||||
//=============
|
||||
seek($FFC0)
|
||||
// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes)
|
||||
db "65816 CPU TEST INC "
|
||||
// "123456789012345678901"
|
||||
|
||||
// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode)
|
||||
db $20
|
||||
// ||___________________Map Mode:
|
||||
// | $X0 = LoROM/32K Banks (Mode 20)
|
||||
// | $X1 = HiROM/64K Banks (Mode 21)
|
||||
// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable)
|
||||
// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable)
|
||||
// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM)
|
||||
// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable)
|
||||
|
||||
// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type)
|
||||
db $00
|
||||
// ||___________________Type:
|
||||
// | $00 = ROM
|
||||
// | $01 = ROM+RAM
|
||||
// Co-processor: $02 = ROM+RAM+Battery
|
||||
// $0X = DSP $X3 = ROM+Co-processor
|
||||
// $1X = GSU $X4 = ROM+Co-processor+RAM
|
||||
// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery
|
||||
// $3X = SA-1 $X6 = ROM+Co-processor+Battery
|
||||
// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513
|
||||
// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked
|
||||
|
||||
// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits)
|
||||
db $01
|
||||
// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit)
|
||||
// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit)
|
||||
// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit)
|
||||
// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit)
|
||||
// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit)
|
||||
// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit)
|
||||
|
||||
// RAM SIZE
|
||||
db $00
|
||||
// $00 = None, $04 = 16Kb
|
||||
// $01 = 2Kb, $05 = 32Kb
|
||||
// $02 = 4Kb, $06 = 64Kb
|
||||
// $03 = 8Kb, $07 = 128Kb
|
||||
|
||||
// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz)
|
||||
db $00
|
||||
// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL)
|
||||
// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL)
|
||||
// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL)
|
||||
// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL)
|
||||
// $04 = Finland (PAL), $0D = South (K)orea (NTSC)
|
||||
// $05 = Denmark (PAL), $0E = (A)Common (ANY)
|
||||
// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC)
|
||||
// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M)
|
||||
// $08 = (S)pain (PAL), $11 = (U)Australia (PAL)
|
||||
|
||||
// DEVELOPER ID CODE
|
||||
db $00
|
||||
// $00 = None
|
||||
// $01 = Nintendo
|
||||
// $33 = New (Uses Extended Header)
|
||||
|
||||
// ROM VERSION NUMBER
|
||||
db $00
|
||||
// $00 = 1.00, $01 = 1.01
|
||||
|
||||
// COMPLEMENT CHECK
|
||||
db "CC"
|
||||
// CHECKSUM
|
||||
db "CS"
|
||||
|
||||
// NATIVE VECTOR (65C816 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (BRK Opcode)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $0000 // RESET VECTOR (Unused)
|
||||
dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt)
|
||||
|
||||
// EMU VECTOR (6502 Mode)
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // RESERVED
|
||||
dw $0000 // COP VECTOR (COP Opcode)
|
||||
dw $0000 // BRK VECTOR (Unused)
|
||||
dw $0000 // ABORT VECTOR (Unused)
|
||||
dw $0000 // NMI VECTOR (V-Blank Interrupt)
|
||||
dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET)
|
||||
dw $0000 // IRQ/BRK VECTOR
|
||||
1
OSBindings/Mac/Clock SignalTests/krom 65816/INC/make.bat
Normal file
1
OSBindings/Mac/Clock SignalTests/krom 65816/INC/make.bat
Normal file
@ -0,0 +1 @@
|
||||
bass CPUINC.asm
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user