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CLK
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574985f9a2
CLK
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Thomas Harte
574985f9a2
Fixed interlaced timing; switched to a more robust detector for horizontal sync; eliminated some test logging.
2016-02-20 20:29:40 -05:00
..
CRT
Fixed interlaced timing; switched to a more robust detector for horizontal sync; eliminated some test logging.
2016-02-20 20:29:40 -05:00
Speaker.cpp
Edging towards audio output; the speaker is given appropriate input and output rates, and then updated with current divider and enabled/disabled status.
2016-01-13 21:03:43 -05:00
Speaker.hpp
Disabled my various bits of rate interchange debugging; improved test for when to call update_display due to a RAM write.
2016-01-21 22:16:52 -05:00