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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-23 03:32:32 +00:00
CLK/Components
2017-08-07 10:36:53 -04:00
..
1770 Fixed WAIT_FOR_TIME macro. 2017-08-06 12:08:54 -04:00
6522
6532
6560
6845 Permitted register 3 to dictate vertical sync length. 2017-08-04 08:56:36 -04:00
8255
8272 Had failed to spot that by taking control of stepping at this level, the appropriate invalidate_tracks were not being sent. 2017-08-07 10:36:53 -04:00
AY38910 Attempted to move to more accurate bus reading — if control lines are set then all subsequent data inputs should act according to the current control lines; changes to port input should be reflected live upon readings, etc. 2017-08-02 19:45:58 -04:00