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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00
CLK/Components
Thomas Harte 7e001c1d03 Corrects data line loading.
Also adds some extra temporary logging. Outstanding question: why is ATN not being signalled? Is SEL enough?
2019-08-17 21:30:59 -04:00
..
1770 Corrects log output. 2019-02-18 20:49:01 -05:00
5380 Corrects data line loading. 2019-08-17 21:30:59 -04:00
6522 Experiments with a JustInTimeActor in the Master System. 2019-07-29 15:38:41 -04:00
6532
6560 Corrects PAL colours for the Vic-20. 2019-02-25 19:28:52 -05:00
6845
8255
8272 Makes an attempt at getting the 5380 past arbitration. 2019-08-15 23:14:40 -04:00
8530 Moves interrupt level selection outside the loop. 2019-07-23 23:13:03 -04:00
9918 Eliminates dangling uses of printf. 2019-03-02 18:07:05 -05:00
AudioToggle
AY38910 Implements proper AY IO output behaviour. 2019-03-05 20:20:26 -05:00
DiskII Makes an attempt at getting the 5380 past arbitration. 2019-08-15 23:14:40 -04:00
KonamiSCC
SN76489