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197 lines
5.5 KiB
C++
197 lines
5.5 KiB
C++
//
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// MemoryMap.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 04/10/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef MemoryMap_hpp
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#define MemoryMap_hpp
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#include "../../Analyser/Static/Amiga/Target.hpp"
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#include <array>
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#include <cassert>
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#include <vector>
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namespace Amiga {
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class MemoryMap {
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private:
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static constexpr auto PermitRead = CPU::MC68000::Microcycle::PermitRead;
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static constexpr auto PermitWrite = CPU::MC68000::Microcycle::PermitWrite;
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static constexpr auto PermitReadWrite = PermitRead | PermitWrite;
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public:
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std::array<uint8_t, 512*1024> kickstart{0xff};
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std::vector<uint8_t> chip_ram{};
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struct MemoryRegion {
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uint8_t *contents = nullptr;
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unsigned int read_write_mask = 0;
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} regions[64]; // i.e. top six bits are used as an index.
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using FastRAM = Analyser::Static::Amiga::Target::FastRAM;
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using ChipRAM = Analyser::Static::Amiga::Target::ChipRAM;
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MemoryMap(ChipRAM chip_ram_size, FastRAM fast_ram_size) {
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// Address spaces that matter:
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//
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// 00'0000 – 08'0000: chip RAM. [or overlayed KickStart]
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// – 10'0000: extended chip ram for ECS.
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// – 20'0000: slow RAM and further chip RAM.
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// – a0'0000: auto-config space (/fast RAM).
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// ...
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// bf'd000 – c0'0000: 8250s.
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// c0'0000 – d8'0000: pseudo-fast RAM.
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// ...
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// dc'0000 – dd'0000: optional real-time clock.
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// df'f000 - e0'0000: custom chip registers.
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// ...
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// f0'0000 — : 512kb Kickstart (or possibly just an extra 512kb reserved for hypothetical 1mb Kickstart?).
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// f8'0000 — : 256kb Kickstart if 2.04 or higher.
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// fc'0000 – : 256kb Kickstart otherwise.
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set_region(0xfc'0000, 0x1'00'0000, kickstart.data(), PermitRead);
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switch(chip_ram_size) {
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default:
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case ChipRAM::FiveHundredAndTwelveKilobytes:
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chip_ram.resize(512 * 1024);
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break;
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case ChipRAM::OneMegabyte:
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chip_ram.resize(1 * 1024 * 1024);
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break;
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case ChipRAM::TwoMegabytes:
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chip_ram.resize(2 * 1024 * 1024);
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break;
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}
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switch(fast_ram_size) {
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default:
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fast_autoconf_visible_ = false;
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break;
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case FastRAM::OneMegabyte:
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fast_ram_.resize(1 * 1024 * 1024);
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fast_ram_size_ = 5;
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break;
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case FastRAM::TwoMegabytes:
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fast_ram_.resize(2 * 1024 * 1024);
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fast_ram_size_ = 6;
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break;
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case FastRAM::FourMegabytes:
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fast_ram_.resize(4 * 1024 * 1024);
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fast_ram_size_ = 7;
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break;
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case FastRAM::EightMegabytes:
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fast_ram_.resize(8 * 1024 * 1024);
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fast_ram_size_ = 0;
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break;
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}
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reset();
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}
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void reset() {
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set_overlay(true);
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}
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void set_overlay(bool enabled) {
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if(overlay_ == enabled) {
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return;
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}
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overlay_ = enabled;
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set_region(0x00'0000, uint32_t(chip_ram.size()), chip_ram.data(), PermitReadWrite);
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if(enabled) {
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set_region(0x00'0000, 0x08'0000, kickstart.data(), PermitRead);
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}
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}
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/// Performs the provided microcycle, which the caller guarantees to be a memory access,
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/// and in the Zorro register range.
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bool perform(const CPU::MC68000::Microcycle &cycle) {
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if(!fast_autoconf_visible_) return false;
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const uint32_t register_address = *cycle.address & 0xfe;
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using Microcycle = CPU::MC68000::Microcycle;
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if(cycle.operation & Microcycle::Read) {
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// Re: Autoconf:
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//
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// "All read registers physically return only the top 4 bits of data, on D31-D28";
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// (this is from Zorro III documentation; I'm assuming it to be D15–D11 for the
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// 68000's 16-bit bus);
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//
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// "Every AUTOCONFIG register is logically considered to be 8 bits wide; the
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// 8 bits actually being nybbles from two paired addresses."
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uint8_t value = 0xf;
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switch(register_address) {
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default: break;
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case 0x00: // er_Type (high)
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value =
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0xc | // Zoro II-style PIC.
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0x2; // Memory will be linked into the free pool
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break;
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case 0x02: // er_Type (low)
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value = fast_ram_size_;
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break;
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// er_Manufacturer
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//
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// On the manufacturer number: this is supposed to be assigned
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// by Commodore. TODO: find and crib a real fast RAM number, if it matters.
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//
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// (0xffff seems to be invalid, so _something_ needs to be supplied)
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case 0x10: case 0x12:
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value = 0xa; // Manufacturer's number, high byte.
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break;
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case 0x14: case 0x16:
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value = 0xb; // Manufacturer's number, low byte.
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break;
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}
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// Shove the value into the top of the data bus.
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cycle.set_value16(uint16_t(0x0fff | (value << 12)));
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} else {
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fast_autoconf_visible_ &= !(register_address >= 0x4c && register_address < 0x50);
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switch(register_address) {
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default: break;
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case 0x48: { // ec_BaseAddress (A23–A16)
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const auto address = uint32_t(cycle.value8_high()) << 16;
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set_region(address, uint32_t(address + fast_ram_.size()), fast_ram_.data(), PermitRead | PermitWrite);
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fast_autoconf_visible_ = false;
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} break;
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}
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}
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return true;
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}
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private:
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std::vector<uint8_t> fast_ram_{};
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uint8_t fast_ram_size_ = 0;
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bool fast_autoconf_visible_ = true;
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bool overlay_ = false;
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void set_region(uint32_t start, uint32_t end, uint8_t *base, unsigned int read_write_mask) {
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[[maybe_unused]] constexpr uint32_t precision_loss_mask = uint32_t(~0xfc'0000);
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assert(!(start & precision_loss_mask));
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assert(!((end - (1 << 18)) & precision_loss_mask));
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assert(end > start);
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if(base) base -= start;
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for(decltype(start) c = start >> 18; c < end >> 18; c++) {
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regions[c].contents = base;
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regions[c].read_write_mask = read_write_mask;
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}
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}
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};
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}
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#endif /* MemoryMap_hpp */
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