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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-10 23:05:01 +00:00
CLK/Components
2017-08-07 19:56:22 -04:00
..
1770 Fixed WAIT_FOR_TIME macro. 2017-08-06 12:08:54 -04:00
6522 Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty. 2017-07-27 22:05:29 -04:00
6532 Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty. 2017-07-27 22:05:29 -04:00
6560 Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty. 2017-07-27 22:05:29 -04:00
6845 Permitted register 3 to dictate vertical sync length. 2017-08-04 08:56:36 -04:00
8255 Added: now declines to pass on output if in input mode for ports A and B. 2017-08-07 19:56:22 -04:00
8272 Prevented the 8272 from overreading ID fields (and, by doing so, overrunning its internal buffer). Exposed the MFMController's CRC generator for inspection. 2017-08-07 12:37:22 -04:00
AY38910 Adjusted: invalid register selection simply deselects all registers. 2017-08-07 19:51:36 -04:00