Add 8080 test runner

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
This commit is contained in:
Adrian.Conlon 2017-06-05 17:31:21 +01:00
parent 8d89f0d98c
commit 4c6f44c394
21 changed files with 4155 additions and 0 deletions

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@ -7,6 +7,8 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "EightBit", "src\EightBit.vc
EndProject
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Intel8080", "Intel8080\src\Intel8080.vcxproj", "{93BDC8D8-9F0D-44ED-94FB-1BE6AC4B6BD6}"
EndProject
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_Intel8080", "Intel8080\test\test_Intel8080.vcxproj", "{391D3B95-D9DA-47E5-9F61-70483F6BB396}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|x64 = Debug|x64
@ -31,6 +33,14 @@ Global
{93BDC8D8-9F0D-44ED-94FB-1BE6AC4B6BD6}.Release|x64.Build.0 = Release|x64
{93BDC8D8-9F0D-44ED-94FB-1BE6AC4B6BD6}.Release|x86.ActiveCfg = Release|Win32
{93BDC8D8-9F0D-44ED-94FB-1BE6AC4B6BD6}.Release|x86.Build.0 = Release|Win32
{391D3B95-D9DA-47E5-9F61-70483F6BB396}.Debug|x64.ActiveCfg = Debug|x64
{391D3B95-D9DA-47E5-9F61-70483F6BB396}.Debug|x64.Build.0 = Debug|x64
{391D3B95-D9DA-47E5-9F61-70483F6BB396}.Debug|x86.ActiveCfg = Debug|Win32
{391D3B95-D9DA-47E5-9F61-70483F6BB396}.Debug|x86.Build.0 = Debug|Win32
{391D3B95-D9DA-47E5-9F61-70483F6BB396}.Release|x64.ActiveCfg = Release|x64
{391D3B95-D9DA-47E5-9F61-70483F6BB396}.Release|x64.Build.0 = Release|x64
{391D3B95-D9DA-47E5-9F61-70483F6BB396}.Release|x86.ActiveCfg = Release|Win32
{391D3B95-D9DA-47E5-9F61-70483F6BB396}.Release|x86.Build.0 = Release|Win32
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE

85
Intel8080/test/Board.cpp Normal file
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#include "stdafx.h"
#include "Board.h"
#include "Disassembler.h"
#include "Configuration.h"
#include <iostream>
Board::Board(const Configuration& configuration)
: m_configuration(configuration),
m_memory(0xffff),
m_cpu(EightBit::Intel8080(m_memory, m_ports)) {
}
void Board::initialise() {
m_memory.clear();
auto romDirectory = m_configuration.getRomDirectory();
//m_memory.loadRam(romDirectory + "/TEST.COM", 0x100); // Microcosm
//m_memory.loadRam(romDirectory + "/8080PRE.COM", 0x100); // Bartholomew preliminary
m_memory.loadRam(romDirectory + "/8080EX1.COM", 0x100); // Cringle/Bartholomew
//m_memory.loadRam(romDirectory + "/CPUTEST.COM", 0x100); // SuperSoft diagnostics
m_memory.set(5, 0xc9); // ret
m_cpu.ExecutingInstruction.connect(std::bind(&Board::Cpu_ExecutingInstruction_Cpm, this, std::placeholders::_1));
if (m_configuration.isProfileMode()) {
m_cpu.ExecutingInstruction.connect(std::bind(&Board::Cpu_ExecutingInstruction_Profile, this, std::placeholders::_1));
}
if (m_configuration.isDebugMode()) {
m_cpu.ExecutingInstruction.connect(std::bind(&Board::Cpu_ExecutingInstruction_Debug, this, std::placeholders::_1));
}
m_cpu.initialise();
m_cpu.setProgramCounter(m_configuration.getStartAddress());
}
void Board::Cpu_ExecutingInstruction_Cpm(const EightBit::Intel8080&) {
auto pc = m_cpu.getProgramCounter();
switch (pc.word) {
case 0x0: // CP/M warm start
m_cpu.halt();
m_profiler.dump();
break;
case 0x5: // BDOS
bdos();
break;
default:
break;
}
}
void Board::bdos() {
auto c = m_cpu.C();
switch (c) {
case 0x2: {
auto character = m_cpu.E();
std::cout << character;
break;
}
case 0x9:
for (uint16_t i = m_cpu.DE().word; m_memory.get(i) != '$'; ++i) {
std::cout << m_memory.get(i);
}
break;
}
}
void Board::Cpu_ExecutingInstruction_Profile(const EightBit::Intel8080& cpu) {
const auto pc = cpu.getProgramCounter();
m_profiler.addAddress(pc.word);
m_profiler.addInstruction(m_memory.peek(pc.word));
}
void Board::Cpu_ExecutingInstruction_Debug(const EightBit::Intel8080&) {
std::cerr
<< EightBit::Disassembler::state(m_cpu)
<< "\t"
<< EightBit::Disassembler::disassemble(m_cpu)
<< '\n';
}

36
Intel8080/test/Board.h Normal file
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#pragma once
//#include <string>
#include "Memory.h"
#include "InputOutput.h"
#include "Intel8080.h"
#include "Profiler.h"
#include "EventArgs.h"
class Configuration;
class Board {
public:
Board(const Configuration& configuration);
EightBit::Memory& getMemory() { return m_memory; }
const EightBit::Intel8080& getCPU() const { return m_cpu; }
EightBit::Intel8080& getCPUMutable() { return m_cpu; }
void initialise();
private:
const Configuration& m_configuration;
EightBit::Memory m_memory;
EightBit::InputOutput m_ports;
EightBit::Intel8080 m_cpu;
EightBit::Profiler m_profiler;
void Cpu_ExecutingInstruction_Cpm(const EightBit::Intel8080& cpu);
void Cpu_ExecutingInstruction_Debug(const EightBit::Intel8080& cpuEvent);
void Cpu_ExecutingInstruction_Profile(const EightBit::Intel8080& cpuEvent);
void bdos();
};

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@ -0,0 +1,8 @@
#include "stdafx.h"
#include "Configuration.h"
Configuration::Configuration()
: m_debugMode(false),
m_profileMode(false),
m_romDirectory("roms") {
}

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@ -0,0 +1,42 @@
#pragma once
#include <string>
#include "Memory.h"
class Configuration {
public:
Configuration();
bool isDebugMode() const {
return m_debugMode;
}
void setDebugMode(bool value) {
m_debugMode = value;
}
bool isProfileMode() const {
return m_profileMode;
}
void setProfileMode(bool value) {
m_profileMode = value;
}
std::string getRomDirectory() const {
return m_romDirectory;
}
EightBit::register16_t getStartAddress() const {
EightBit::register16_t returned;
returned.word = 0x100;
return returned;
}
private:
bool m_debugMode;
bool m_profileMode;
std::string m_romDirectory;
};

21
Intel8080/test/Game.cpp Normal file
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#include "stdafx.h"
#include "Game.h"
#include <algorithm>
Game::Game(const Configuration& configuration)
: m_configuration(configuration),
m_board(configuration) {
}
void Game::initialise() {
m_board.initialise();
}
void Game::runLoop() {
auto& cpu = m_board.getCPUMutable();
auto cycles = 0;
while (!cpu.isHalted()) {
cycles = cpu.step();
}
}

22
Intel8080/test/Game.h Normal file
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@ -0,0 +1,22 @@
#pragma once
//#include <stdexcept>
//#include <string>
//#include <memory>
//#include <map>
#include "Board.h"
class Configuration;
class Game {
public:
Game(const Configuration& configuration);
void runLoop();
void initialise();
private:
const Configuration& m_configuration;
mutable Board m_board;
};

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@ -0,0 +1,291 @@
title 'Preliminary Z80 tests'
; prelim.z80 - Preliminary Z80 tests
; Copyright (C) 1994 Frank D. Cringle
;
; This program is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License
; as published by the Free Software Foundation; either version 2
; of the License, or (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
; These tests have two goals. To start with, we assume the worst and
; successively test the instructions needed to continue testing.
; Then we try to test all instructions which cannot be handled by
; zexlax - the crc-based instruction exerciser.
; Initially errors are 'reported' by jumping to 0. This should reboot
; cp/m, so if the program terminates without any output one of the
; early tests failed. Later errors are reported by outputting an
; address via the bdos conout routine. The address can be located in
; a listing of this program.
; If the program runs to completion it displays a suitable message.
;******************************************************************************
;
; Modified by Ian Bartholomew to run a preliminary test on an 8080 CPU
;
; Assemble using M80
;
;******************************************************************************
.8080
aseg
org 100h
start: mvi a,1 ; test simple compares and z/nz jumps
cpi 2
jz 0
cpi 1
jnz 0
jmp lab0
hlt ; emergency exit
db 0ffh
lab0: call lab2 ; does a simple call work?
lab1: jmp 0 ; fail
lab2: pop h ; check return address
mov a,h
cpi high lab1
jz lab3
jmp 0
lab3: mov a,l
cpi low lab1
jz lab4
jmp 0
; test presence and uniqueness of all machine registers
; (except ir)
lab4: lxi sp,regs1
pop psw
pop b
pop d
pop h
lxi sp,regs2+8
push h
push d
push b
push psw
v defl 0
rept 8
lda regs2+v/2
v defl v+2
cpi v
jnz 0
endm
; test access to memory via (hl)
lxi h,hlval
mov a,m
cpi 0a5h
jnz 0
lxi h,hlval+1
mov a,m
cpi 03ch
jnz 0
; test unconditional return
lxi sp,stack
lxi h,reta
push h
ret
jmp 0
; test instructions needed for hex output
reta: mvi a,0ffh
ani 0fh
cpi 0fh
jnz 0
mvi a,05ah
ani 0fh
cpi 0ah
jnz 0
rrc
cpi 05h
jnz 0
rrc
cpi 82h
jnz 0
rrc
cpi 41h
jnz 0
rrc
cpi 0a0h
jnz 0
lxi h,01234h
push h
pop b
mov a,b
cpi 12h
jnz 0
mov a,c
cpi 34h
jnz 0
; from now on we can report errors by displaying an address
; test conditional call, ret, jp, jr
tcond macro flag,pcond,ncond,rel
lxi h,&flag
push h
pop psw
c&pcond lab1&pcond
jmp error
lab1&pcond: pop h
lxi h,0d7h xor &flag
push h
pop psw
c&ncond lab2&pcond
jmp error
lab2&pcond: pop h
lxi h,lab3&pcond
push h
lxi h,&flag
push h
pop psw
r&pcond
call error
lab3&pcond: lxi h,lab4&pcond
push h
lxi h,0d7h xor &flag
push h
pop psw
r&ncond
call error
lab4&pcond: lxi h,&flag
push h
pop psw
j&pcond lab5&pcond
call error
lab5&pcond: lxi h,0d7h xor &flag
push h
pop psw
j&ncond lab6&pcond
call error
lab6&pcond:
endm
tcond 1,c,nc,1
tcond 4,pe,po,0
tcond 040h,z,nz,1
tcond 080h,m,p,0
; test indirect jumps
lxi h,lab7
pchl
call error
; djnz (and (partially) inc a, inc hl)
lab7: mvi a,0a5h
mvi b,4
lab8: rrc
dcr b
jnz lab8
cpi 05ah
cnz error
mvi b,16
lab9: inr a
dcr b
jnz lab9
cpi 06ah
cnz error
mvi b,0
lxi h,0
lab10: inx h
dcr b
jnz lab10
mov a,h
cpi 1
cnz error
mov a,l
cpi 0
cnz error
allok: lxi d,okmsg
mvi c,9
call 5
jmp 0
okmsg: db '8080 Preliminary tests complete$'
; display address at top of stack and exit
error: pop b
mvi h,high hextab
mov a,b
rrc
rrc
rrc
rrc
ani 15
mov l,a
mov a,m
call conout
mov a,b
ani 15
mov l,a
mov a,m
call conout
mov a,c
rrc
rrc
rrc
rrc
ani 15
mov l,a
mov a,m
call conout
mov a,c
ani 15
mov l,a
mov a,m
call conout
mvi a,13
call conout
mvi a,10
call conout
jmp 0
conout: push psw
push b
push d
push h
mvi c,2
mov e,a
call 5
pop h
pop d
pop b
pop psw
ret
v defl 0
regs1: rept 8
v defl v+2
db v
endm
regs2: ds 8,0
hlval: db 0a5h,03ch
; skip to next page boundary
org (($+255)/256)*256
hextab: db '0123456789abcdef'
ds 240
stack equ $
end start

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@ -0,0 +1,805 @@
;***********************************************************************
; MICROCOSM ASSOCIATES 8080/8085 CPU DIAGNOSTIC VERSION 1.0 (C) 1980
;***********************************************************************
; Load into virtual altair with: ALTAIR L=TEST.HEX
; Then press F2 to view screen, and 'G' to execute the test.
;
;DONATED TO THE "SIG/M" CP/M USER'S GROUP BY:
;KELLY SMITH, MICROCOSM ASSOCIATES
;3055 WACO AVENUE
;SIMI VALLEY, CALIFORNIA, 93065
;(805) 527-9321 (MODEM, CP/M-NET (TM))
;(805) 527-0518 (VERBAL)
;
CPU 8080
ORG 00100H
LXI H, LOLZ
CALL MSG
JMP CPU ;JUMP TO 8080 CPU DIAGNOSTIC
;
LOLZ: DB "MICROCOSM ASSOCIATES 8080/8085 CPU DIAGNOSTIC VERSION 1.0 (C) 1980", 0dh, 0ah, 24h
;
BDOS EQU 00005H ;BDOS ENTRY TO CP/M
WBOOT: JMP 0
;
;MESSAGE OUTPUT ROUTINE
;
MSG: MOV A,M ; Get data
CPI '$' ; End?
RZ
CALL PCHAR ; Output
INX H ; Next
JMP MSG ; Do all
;
;
;CHARACTER OUTPUT ROUTINE
;
PCHAR: PUSH PSW
PUSH D
PUSH H
MOV E,A
MVI C,2
CALL BDOS
POP H
POP D
POP PSW
RET
;
;
;
BYTEO: PUSH PSW
CALL BYTO1
MOV E,A
CALL PCHAR
POP PSW
CALL BYTO2
MOV E,A
JMP PCHAR
BYTO1: RRC
RRC
RRC
RRC
BYTO2: ANI 0FH
CPI 0AH
JM BYTO3
ADI 7
BYTO3: ADI 30H
RET
;
;
;
;************************************************************
; MESSAGE TABLE FOR OPERATIONAL CPU TEST
;************************************************************
;
OKCPU: DB 0DH,0AH
DB "CPU IS OPERATIONAL$"
;
NGCPU: DB 0DH,0AH
DB " CPU HAS FAILED! ERROR EXIT=$"
;
;
;
;************************************************************
; 8080/8085 CPU TEST/DIAGNOSTIC
;************************************************************
;
;NOTE: (1) PROGRAM ASSUMES "CALL",AND "LXI SP" INSTRUCTIONS WORK!
;
; (2) INSTRUCTIONS NOT TESTED ARE "HLT","DI","EI",
; AND "RST 0" THRU "RST 7"
;
;
;
;TEST JUMP INSTRUCTIONS AND FLAGS
;
CPU: LXI SP,STACK ;SET THE STACK POINTER
ANI 0 ;INITIALIZE A REG. AND CLEAR ALL FLAGS
JZ J010 ;TEST "JZ"
CALL CPUER
J010: JNC J020 ;TEST "JNC"
CALL CPUER
J020: JPE J030 ;TEST "JPE"
CALL CPUER
J030: JP J040 ;TEST "JP"
CALL CPUER
J040: JNZ J050 ;TEST "JNZ"
JC J050 ;TEST "JC"
JPO J050 ;TEST "JPO"
JM J050 ;TEST "JM"
JMP J060 ;TEST "JMP" (IT'S A LITTLE LATE,BUT WHAT THE HELL!
J050: CALL CPUER
J060: ADI 6 ;A=6,C=0,P=1,S=0,Z=0
JNZ J070 ;TEST "JNZ"
CALL CPUER
J070: JC J080 ;TEST "JC"
JPO J080 ;TEST "JPO"
JP J090 ;TEST "JP"
J080: CALL CPUER
J090: ADI 070H ;A=76H,C=0,P=0,S=0,Z=0
JPO J100 ;TEST "JPO"
CALL CPUER
J100: JM J110 ;TEST "JM"
JZ J110 ;TEST "JZ"
JNC J120 ;TEST "JNC"
J110: CALL CPUER
J120: ADI 081H ;A=F7H,C=0,P=0,S=1,Z=0
JM J130 ;TEST "JM"
CALL CPUER
J130: JZ J140 ;TEST "JZ"
JC J140 ;TEST "JC"
JPO J150 ;TEST "JPO"
J140: CALL CPUER
J150: ADI 0FEH ;A=F5H,C=1,P=1,S=1,Z=0
JC J160 ;TEST "JC"
CALL CPUER
J160: JZ J170 ;TEST "JZ"
JPO J170 ;TEST "JPO"
JM AIMM ;TEST "JM"
J170: CALL CPUER
;
;
;
;TEST ACCUMULATOR IMMEDIATE INSTRUCTIONS
;
AIMM: CPI 0 ;A=F5H,C=0,Z=0
JC CPIE ;TEST "CPI" FOR RE-SET CARRY
JZ CPIE ;TEST "CPI" FOR RE-SET ZERO
CPI 0F5H ;A=F5H,C=0,Z=1
JC CPIE ;TEST "CPI" FOR RE-SET CARRY ("ADI")
JNZ CPIE ;TEST "CPI" FOR RE-SET ZERO
CPI 0FFH ;A=F5H,C=1,Z=0
JZ CPIE ;TEST "CPI" FOR RE-SET ZERO
JC ACII ;TEST "CPI" FOR SET CARRY
CPIE: CALL CPUER
ACII: ACI 00AH ;A=F5H+0AH+CARRY(1)=0,C=1
ACI 00AH ;A=0+0AH+CARRY(0)=0BH,C=0
CPI 00BH
JZ SUII ;TEST "ACI"
CALL CPUER
SUII: SUI 00CH ;A=FFH,C=0
SUI 00FH ;A=F0H,C=1
CPI 0F0H
JZ SBII ;TEST "SUI"
CALL CPUER
SBII: SBI 0F1H ;A=F0H-0F1H-CARRY(0)=FFH,C=1
SBI 00EH ;A=FFH-OEH-CARRY(1)=F0H,C=0
CPI 0F0H
JZ ANII ;TEST "SBI"
CALL CPUER
ANII: ANI 055H ;A=F0H<AND>55H=50H,C=0,P=1,S=0,Z=0
CPI 050H
JZ ORII ;TEST "ANI"
CALL CPUER
ORII: ORI 03AH ;A=50H<OR>3AH=7AH,C=0,P=0,S=0,Z=0
CPI 07AH
JZ XRII ;TEST "ORI"
CALL CPUER
XRII: XRI 00FH ;A=7AH<XOR>0FH=75H,C=0,P=0,S=0,Z=0
CPI 075H
JZ C010 ;TEST "XRI"
CALL CPUER
;
;
;
;TEST CALLS AND RETURNS
;
C010: ANI 000H ;A=0,C=0,P=1,S=0,Z=1
CC CPUER ;TEST "CC"
CPO CPUER ;TEST "CPO"
CM CPUER ;TEST "CM"
CNZ CPUER ;TEST "CNZ"
CPI 000H
JZ C020 ;A=0,C=0,P=0,S=0,Z=1
CALL CPUER
C020: SUI 077H ;A=89H,C=1,P=0,S=1,Z=0
CNC CPUER ;TEST "CNC"
CPE CPUER ;TEST "CPE"
CP CPUER ;TEST "CP"
CZ CPUER ;TEST "CZ"
CPI 089H
JZ C030 ;TEST FOR "CALLS" TAKING BRANCH
CALL CPUER
C030: ANI 0FFH ;SET FLAGS BACK!
CPO CPOI ;TEST "CPO"
CPI 0D9H
JZ MOVI ;TEST "CALL" SEQUENCE SUCCESS
CALL CPUER
CPOI: RPE ;TEST "RPE"
ADI 010H ;A=99H,C=0,P=0,S=1,Z=0
CPE CPEI ;TEST "CPE"
ADI 002H ;A=D9H,C=0,P=0,S=1,Z=0
RPO ;TEST "RPO"
CALL CPUER
CPEI: RPO ;TEST "RPO"
ADI 020H ;A=B9H,C=0,P=0,S=1,Z=0
CM CMI ;TEST "CM"
ADI 004H ;A=D7H,C=0,P=1,S=1,Z=0
RPE ;TEST "RPE"
CALL CPUER
CMI: RP ;TEST "RP"
ADI 080H ;A=39H,C=1,P=1,S=0,Z=0
CP TCPI ;TEST "CP"
ADI 080H ;A=D3H,C=0,P=0,S=1,Z=0
RM ;TEST "RM"
CALL CPUER
TCPI: RM ;TEST "RM"
ADI 040H ;A=79H,C=0,P=0,S=0,Z=0
CNC CNCI ;TEST "CNC"
ADI 040H ;A=53H,C=0,P=1,S=0,Z=0
RP ;TEST "RP"
CALL CPUER
CNCI: RC ;TEST "RC"
ADI 08FH ;A=08H,C=1,P=0,S=0,Z=0
CC CCI ;TEST "CC"
SUI 002H ;A=13H,C=0,P=0,S=0,Z=0
RNC ;TEST "RNC"
CALL CPUER
CCI: RNC ;TEST "RNC"
ADI 0F7H ;A=FFH,C=0,P=1,S=1,Z=0
CNZ CNZI ;TEST "CNZ"
ADI 0FEH ;A=15H,C=1,P=0,S=0,Z=0
RC ;TEST "RC"
CALL CPUER
CNZI: RZ ;TEST "RZ"
ADI 001H ;A=00H,C=1,P=1,S=0,Z=1
CZ CZI ;TEST "CZ"
ADI 0D0H ;A=17H,C=1,P=1,S=0,Z=0
RNZ ;TEST "RNZ"
CALL CPUER
CZI: RNZ ;TEST "RNZ"
ADI 047H ;A=47H,C=0,P=1,S=0,Z=0
CPI 047H ;A=47H,C=0,P=1,S=0,Z=1
RZ ;TEST "RZ"
CALL CPUER
;
;
;
;TEST "MOV","INR",AND "DCR" INSTRUCTIONS
;
MOVI: MVI A,077H
INR A
MOV B,A
INR B
MOV C,B
DCR C
MOV D,C
MOV E,D
MOV H,E
MOV L,H
MOV A,L ;TEST "MOV" A,L,H,E,D,C,B,A
DCR A
MOV C,A
MOV E,C
MOV L,E
MOV B,L
MOV D,B
MOV H,D
MOV A,H ;TEST "MOV" A,H,D,B,L,E,C,A
MOV D,A
INR D
MOV L,D
MOV C,L
INR C
MOV H,C
MOV B,H
DCR B
MOV E,B
MOV A,E ;TEST "MOV" A,E,B,H,C,L,D,A
MOV E,A
INR E
MOV B,E
MOV H,B
INR H
MOV C,H
MOV L,C
MOV D,L
DCR D
MOV A,D ;TEST "MOV" A,D,L,C,H,B,E,A
MOV H,A
DCR H
MOV D,H
MOV B,D
MOV L,B
INR L
MOV E,L
DCR E
MOV C,E
MOV A,C ;TEST "MOV" A,C,E,L,B,D,H,A
MOV L,A
DCR L
MOV H,L
MOV E,H
MOV D,E
MOV C,D
MOV B,C
MOV A,B
CPI 077H
CNZ CPUER ;TEST "MOV" A,B,C,D,E,H,L,A
;
;
;
;TEST ARITHMETIC AND LOGIC INSTRUCTIONS
;
XRA A
MVI B,001H
MVI C,003H
MVI D,007H
MVI E,00FH
MVI H,01FH
MVI L,03FH
ADD B
ADD C
ADD D
ADD E
ADD H
ADD L
ADD A
CPI 0F0H
CNZ CPUER ;TEST "ADD" B,C,D,E,H,L,A
SUB B
SUB C
SUB D
SUB E
SUB H
SUB L
CPI 078H
CNZ CPUER ;TEST "SUB" B,C,D,E,H,L
SUB A
CNZ CPUER ;TEST "SUB" A
MVI A,080H
ADD A
MVI B,001H
MVI C,002H
MVI D,003H
MVI E,004H
MVI H,005H
MVI L,006H
ADC B
MVI B,080H
ADD B
ADD B
ADC C
ADD B
ADD B
ADC D
ADD B
ADD B
ADC E
ADD B
ADD B
ADC H
ADD B
ADD B
ADC L
ADD B
ADD B
ADC A
CPI 037H
CNZ CPUER ;TEST "ADC" B,C,D,E,H,L,A
MVI A,080H
ADD A
MVI B,001H
SBB B
MVI B,0FFH
ADD B
SBB C
ADD B
SBB D
ADD B
SBB E
ADD B
SBB H
ADD B
SBB L
CPI 0E0H
CNZ CPUER ;TEST "SBB" B,C,D,E,H,L
MVI A,080H
ADD A
SBB A
CPI 0FFH
CNZ CPUER ;TEST "SBB" A
MVI A,0FFH
MVI B,0FEH
MVI C,0FCH
MVI D,0EFH
MVI E,07FH
MVI H,0F4H
MVI L,0BFH
ANA A
ANA C
ANA D
ANA E
ANA H
ANA L
ANA A
CPI 024H
CNZ CPUER ;TEST "ANA" B,C,D,E,H,L,A
XRA A
MVI B,001H
MVI C,002H
MVI D,004H
MVI E,008H
MVI H,010H
MVI L,020H
ORA B
ORA C
ORA D
ORA E
ORA H
ORA L
ORA A
CPI 03FH
CNZ CPUER ;TEST "ORA" B,C,D,E,H,L,A
MVI A,000H
MVI H,08FH
MVI L,04FH
XRA B
XRA C
XRA D
XRA E
XRA H
XRA L
CPI 0CFH
CNZ CPUER ;TEST "XRA" B,C,D,E,H,L
XRA A
CNZ CPUER ;TEST "XRA" A
MVI B,044H
MVI C,045H
MVI D,046H
MVI E,047H
MVI H,(TEMP0/0FFH) ;HIGH BYTE OF TEST MEMORY LOCATION
MVI L,(TEMP0&0FFH) ;LOW BYTE OF TEST MEMORY LOCATION
MOV M,B
MVI B,000H
MOV B,M
MVI A,044H
CMP B
CNZ CPUER ;TEST "MOV" M,B AND B,M
MOV M,D
MVI D,000H
MOV D,M
MVI A,046H
CMP D
CNZ CPUER ;TEST "MOV" M,D AND D,M
MOV M,E
MVI E,000H
MOV E,M
MVI A,047H
CMP E
CNZ CPUER ;TEST "MOV" M,E AND E,M
MOV M,H
MVI H,(TEMP0/0FFH)
MVI L,(TEMP0&0FFH)
MOV H,M
MVI A,(TEMP0/0FFH)
CMP H
CNZ CPUER ;TEST "MOV" M,H AND H,M
MOV M,L
MVI H,(TEMP0/0FFH)
MVI L,(TEMP0&0FFH)
MOV L,M
MVI A,(TEMP0&0FFH)
CMP L
CNZ CPUER ;TEST "MOV" M,L AND L,M
MVI H,(TEMP0/0FFH)
MVI L,(TEMP0&0FFH)
MVI A,032H
MOV M,A
CMP M
CNZ CPUER ;TEST "MOV" M,A
ADD M
CPI 064H
CNZ CPUER ;TEST "ADD" M
XRA A
MOV A,M
CPI 032H
CNZ CPUER ;TEST "MOV" A,M
MVI H,(TEMP0/0FFH)
MVI L,(TEMP0&0FFH)
MOV A,M
SUB M
CNZ CPUER ;TEST "SUB" M
MVI A,080H
ADD A
ADC M
CPI 033H
CNZ CPUER ;TEST "ADC" M
MVI A,080H
ADD A
SBB M
CPI 0CDH
CNZ CPUER ;TEST "SBB" M
ANA M
CNZ CPUER ;TEST "ANA" M
MVI A,025H
ORA M
CPI 037H
CNZ CPUER ;TEST "ORA" M
XRA M
CPI 005H
CNZ CPUER ;TEST "XRA" M
MVI M,055H
INR M
DCR M
ADD M
CPI 05AH
CNZ CPUER ;TEST "INR","DCR",AND "MVI" M
LXI B,12FFH
LXI D,12FFH
LXI H,12FFH
INX B
INX D
INX H
MVI A,013H
CMP B
CNZ CPUER ;TEST "LXI" AND "INX" B
CMP D
CNZ CPUER ;TEST "LXI" AND "INX" D
CMP H
CNZ CPUER ;TEST "LXI" AND "INX" H
MVI A,000H
CMP C
CNZ CPUER ;TEST "LXI" AND "INX" B
CMP E
CNZ CPUER ;TEST "LXI" AND "INX" D
CMP L
CNZ CPUER ;TEST "LXI" AND "INX" H
DCX B
DCX D
DCX H
MVI A,012H
CMP B
CNZ CPUER ;TEST "DCX" B
CMP D
CNZ CPUER ;TEST "DCX" D
CMP H
CNZ CPUER ;TEST "DCX" H
MVI A,0FFH
CMP C
CNZ CPUER ;TEST "DCX" B
CMP E
CNZ CPUER ;TEST "DCX" D
CMP L
CNZ CPUER ;TEST "DCX" H
STA TEMP0
XRA A
LDA TEMP0
CPI 0FFH
CNZ CPUER ;TEST "LDA" AND "STA"
LHLD TEMPP
SHLD TEMP0
LDA TEMPP
MOV B,A
LDA TEMP0
CMP B
CNZ CPUER ;TEST "LHLD" AND "SHLD"
LDA TEMPP+1
MOV B,A
LDA TEMP0+1
CMP B
CNZ CPUER ;TEST "LHLD" AND "SHLD"
MVI A,0AAH
STA TEMP0
MOV B,H
MOV C,L
XRA A
LDAX B
CPI 0AAH
CNZ CPUER ;TEST "LDAX" B
INR A
STAX B
LDA TEMP0
CPI 0ABH
CNZ CPUER ;TEST "STAX" B
MVI A,077H
STA TEMP0
LHLD TEMPP
LXI D,00000H
XCHG
XRA A
LDAX D
CPI 077H
CNZ CPUER ;TEST "LDAX" D AND "XCHG"
XRA A
ADD H
ADD L
CNZ CPUER ;TEST "XCHG"
MVI A,0CCH
STAX D
LDA TEMP0
CPI 0CCH
STAX D
LDA TEMP0
CPI 0CCH
CNZ CPUER ;TEST "STAX" D
LXI H,07777H
DAD H
MVI A,0EEH
CMP H
CNZ CPUER ;TEST "DAD" H
CMP L
CNZ CPUER ;TEST "DAD" H
LXI H,05555H
LXI B,0FFFFH
DAD B
MVI A,055H
CNC CPUER ;TEST "DAD" B
CMP H
CNZ CPUER ;TEST "DAD" B
MVI A,054H
CMP L
CNZ CPUER ;TEST "DAD" B
LXI H,0AAAAH
LXI D,03333H
DAD D
MVI A,0DDH
CMP H
CNZ CPUER ;TEST "DAD" D
CMP L
CNZ CPUER ;TEST "DAD" B
STC
CNC CPUER ;TEST "STC"
CMC
CC CPUER ;TEST "CMC
MVI A,0AAH
CMA
CPI 055H
CNZ CPUER ;TEST "CMA"
ORA A ;RE-SET AUXILIARY CARRY
DAA
CPI 055H
CNZ CPUER ;TEST "DAA"
MVI A,088H
ADD A
DAA
CPI 076H
CNZ CPUER ;TEST "DAA"
XRA A
MVI A,0AAH
DAA
CNC CPUER ;TEST "DAA"
CPI 010H
CNZ CPUER ;TEST "DAA"
XRA A
MVI A,09AH
DAA
CNC CPUER ;TEST "DAA"
CNZ CPUER ;TEST "DAA"
STC
MVI A,042H
RLC
CC CPUER ;TEST "RLC" FOR RE-SET CARRY
RLC
CNC CPUER ;TEST "RLC" FOR SET CARRY
CPI 009H
CNZ CPUER ;TEST "RLC" FOR ROTATION
RRC
CNC CPUER ;TEST "RRC" FOR SET CARRY
RRC
CPI 042H
CNZ CPUER ;TEST "RRC" FOR ROTATION
RAL
RAL
CNC CPUER ;TEST "RAL" FOR SET CARRY
CPI 008H
CNZ CPUER ;TEST "RAL" FOR ROTATION
RAR
RAR
CC CPUER ;TEST "RAR" FOR RE-SET CARRY
CPI 002H
CNZ CPUER ;TEST "RAR" FOR ROTATION
LXI B,01234H
LXI D,0AAAAH
LXI H,05555H
XRA A
PUSH B
PUSH D
PUSH H
PUSH PSW
LXI B,00000H
LXI D,00000H
LXI H,00000H
MVI A,0C0H
ADI 0F0H
POP PSW
POP H
POP D
POP B
CC CPUER ;TEST "PUSH PSW" AND "POP PSW"
CNZ CPUER ;TEST "PUSH PSW" AND "POP PSW"
CPO CPUER ;TEST "PUSH PSW" AND "POP PSW"
CM CPUER ;TEST "PUSH PSW" AND "POP PSW"
MVI A,012H
CMP B
CNZ CPUER ;TEST "PUSH B" AND "POP B"
MVI A,034H
CMP C
CNZ CPUER ;TEST "PUSH B" AND "POP B"
MVI A,0AAH
CMP D
CNZ CPUER ;TEST "PUSH D" AND "POP D"
CMP E
CNZ CPUER ;TEST "PUSH D" AND "POP D"
MVI A,055H
CMP H
CNZ CPUER ;TEST "PUSH H" AND "POP H"
CMP L
CNZ CPUER ;TEST "PUSH H" AND "POP H"
LXI H,00000H
DAD SP
SHLD SAVSTK ;SAVE THE "OLD" STACK-POINTER!
LXI SP,TEMP4
DCX SP
DCX SP
INX SP
DCX SP
MVI A,055H
STA TEMP2
CMA
STA TEMP3
POP B
CMP B
CNZ CPUER ;TEST "LXI","DAD","INX",AND "DCX" SP
CMA
CMP C
CNZ CPUER ;TEST "LXI","DAD","INX", AND "DCX" SP
LXI H,TEMP4
SPHL
LXI H,07733H
DCX SP
DCX SP
XTHL
LDA TEMP3
CPI 077H
CNZ CPUER ;TEST "SPHL" AND "XTHL"
LDA TEMP2
CPI 033H
CNZ CPUER ;TEST "SPHL" AND "XTHL"
MVI A,055H
CMP L
CNZ CPUER ;TEST "SPHL" AND "XTHL"
CMA
CMP H
CNZ CPUER ;TEST "SPHL" AND "XTHL"
LHLD SAVSTK ;RESTORE THE "OLD" STACK-POINTER
SPHL
LXI H,CPUOK
PCHL ;TEST "PCHL"
;
;
;
CPUER: LXI H,NGCPU ;OUTPUT "CPU HAS FAILED ERROR EXIT=" TO CONSOLE
CALL MSG
XTHL
MOV A,H
CALL BYTEO ;SHOW ERROR EXIT ADDRESS HIGH BYTE
MOV A,L
CALL BYTEO ;SHOW ERROR EXIT ADDRESS LOW BYTE
JMP WBOOT ;EXIT TO CP/M WARM BOOT
;
;
;
CPUOK: LXI H,OKCPU ;OUTPUT "CPU IS OPERATIONAL" TO CONSOLE
CALL MSG
JMP WBOOT ;EXIT TO CP/M WARM BOOT
;
;
;
TEMPP: DW TEMP0 ;POINTER USED TO TEST "LHLD","SHLD",
; AND "LDAX" INSTRUCTIONS
;
TEMP0: DS 1 ;TEMPORARY STORAGE FOR CPU TEST MEMORY LOCATIONS
TEMP1: DS 1 ;TEMPORARY STORAGE FOR CPU TEST MEMORY LOCATIONS
TEMP2 DS 1 ;TEMPORARY STORAGE FOR CPU TEST MEMORY LOCATIONS
TEMP3: DS 1 ;TEMPORARY STORAGE FOR CPU TEST MEMORY LOCATIONS
TEMP4: DS 1 ;TEMPORARY STORAGE FOR CPU TEST MEMORY LOCATIONS
SAVSTK: DS 2 ;TEMPORARY STACK-POINTER STORAGE LOCATION
;
;
;
STACK EQU TEMPP+256 ;DE-BUG STACK POINTER STORAGE AREA
;
END

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@ -0,0 +1 @@
#include "stdafx.h"

24
Intel8080/test/stdafx.h Normal file
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@ -0,0 +1,24 @@
#ifdef _MSC_VER
#pragma once
#endif
#include <string>
#include <cstdint>
#include <stdexcept>
#include <algorithm>
#include <memory>
#include <iostream>
#include <array>
#include <vector>
#include <map>
//#include <SDL.h>
//#include <SDL_mixer.h>
//
//#ifdef _MSC_VER
//#pragma comment(lib, "SDL2.lib")
//#pragma comment(lib, "SDL2main.lib")
//#pragma comment(lib, "SDL2_mixer.lib")
//#endif

19
Intel8080/test/test.cpp Normal file
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@ -0,0 +1,19 @@
#include "stdafx.h"
#include "Game.h"
#include "Configuration.h"
int main(int, char*[]) {
Configuration configuration;
#ifdef _DEBUG
configuration.setDebugMode(true);
configuration.setProfileMode(true);
#endif
Game game(configuration);
game.initialise();
game.runLoop();
return 0;
}

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@ -0,0 +1,177 @@
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View File

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