mirror of
https://github.com/MoleskiCoder/EightBit.git
synced 2024-12-12 03:30:07 +00:00
Move to an event driven clock tick event for all CPUs
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
This commit is contained in:
Adrian Conlon
parent
8b187e7614
commit
68030610d8
@ -26,7 +26,7 @@ EightBit::register16_t& EightBit::Intel8080::HL() {
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void EightBit::Intel8080::handleRESET() {
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IntelProcessor::handleRESET();
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di();
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addCycles(3);
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tick(3);
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}
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@ -37,7 +37,7 @@ void EightBit::Intel8080::handleINT() {
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di();
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Processor::execute(BUS().DATA());
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}
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addCycles(3);
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tick(3);
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}
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void EightBit::Intel8080::di() {
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@ -308,7 +308,7 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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case 0: // Relative jumps and assorted ops
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switch (y) {
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case 0: // NOP
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addCycles(4);
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tick(4);
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break;
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}
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break;
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@ -316,11 +316,11 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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switch (q) {
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case 0: // LD rp,nn
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RP(p) = fetchWord();
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addCycles(10);
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tick(10);
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break;
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case 1: // ADD HL,rp
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add(RP(p));
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addCycles(11);
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tick(11);
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break;
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default:
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UNREACHABLE;
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@ -332,21 +332,21 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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switch (p) {
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case 0: // LD (BC),A
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BUS().write(BC(), A());
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addCycles(7);
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tick(7);
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break;
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case 1: // LD (DE),A
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BUS().write(DE(), A());
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addCycles(7);
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tick(7);
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break;
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case 2: // LD (nn),HL
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BUS().ADDRESS() = fetchWord();
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setWord(HL());
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addCycles(16);
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tick(16);
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break;
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case 3: // LD (nn),A
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BUS().ADDRESS() = fetchWord();
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BUS().write(A());
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addCycles(13);
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tick(13);
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break;
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default:
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UNREACHABLE;
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@ -356,21 +356,21 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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switch (p) {
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case 0: // LD A,(BC)
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A() = BUS().read(BC());
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addCycles(7);
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tick(7);
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break;
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case 1: // LD A,(DE)
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A() = BUS().read(DE());
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addCycles(7);
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tick(7);
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break;
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case 2: // LD HL,(nn)
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BUS().ADDRESS() = fetchWord();
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HL() = getWord();
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addCycles(16);
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tick(16);
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break;
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case 3: // LD A,(nn)
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BUS().ADDRESS() = fetchWord();
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A() = BUS().read();
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addCycles(13);
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tick(13);
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break;
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default:
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UNREACHABLE;
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@ -391,27 +391,27 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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default:
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UNREACHABLE;
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}
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addCycles(6);
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tick(6);
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break;
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case 4: { // 8-bit INC
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auto operand = R(y);
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increment(operand);
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R(y, operand);
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addCycles(4);
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tick(4);
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break;
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} case 5: { // 8-bit DEC
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auto operand = R(y);
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decrement(operand);
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R(y, operand);
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addCycles(4);
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tick(4);
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if (UNLIKELY(y == 6))
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addCycles(7);
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tick(7);
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break;
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} case 6: // 8-bit load immediate
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R(y, fetchByte());
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addCycles(7);
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tick(7);
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if (UNLIKELY(y == 6))
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addCycles(3);
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tick(3);
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y) {
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@ -442,7 +442,7 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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default:
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UNREACHABLE;
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}
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addCycles(4);
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tick(4);
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break;
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default:
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UNREACHABLE;
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@ -454,9 +454,9 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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} else {
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R(y, R(z));
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if (UNLIKELY((y == 6) || (z == 6))) // M operations
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addCycles(3);
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tick(3);
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}
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addCycles(4);
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tick(4);
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break;
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case 2: // Operate on accumulator and register/memory location
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switch (y) {
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@ -487,36 +487,36 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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default:
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UNREACHABLE;
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}
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addCycles(4);
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tick(4);
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if (UNLIKELY(z == 6))
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addCycles(3);
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tick(3);
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break;
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case 3:
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switch (z) {
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case 0: // Conditional return
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if (returnConditionalFlag(y))
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addCycles(6);
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addCycles(5);
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tick(6);
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tick(5);
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break;
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case 1: // POP & various ops
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switch (q) {
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case 0: // POP rp2[p]
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RP2(p) = popWord();
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addCycles(10);
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tick(10);
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break;
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case 1:
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switch (p) {
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case 0: // RET
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ret();
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addCycles(10);
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tick(10);
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break;
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case 2: // JP HL
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jump(HL());
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addCycles(4);
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tick(4);
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break;
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case 3: // LD SP,HL
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SP() = HL();
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addCycles(4);
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tick(4);
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break;
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}
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break;
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@ -526,56 +526,56 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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break;
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case 2: // Conditional jump
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jumpConditionalFlag(y);
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addCycles(10);
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tick(10);
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break;
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case 3: // Assorted operations
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switch (y) {
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case 0: // JP nn
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jump(fetchWord());
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addCycles(10);
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tick(10);
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break;
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case 2: // OUT (n),A
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writePort(fetchByte());
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addCycles(11);
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tick(11);
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break;
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case 3: // IN A,(n)
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A() = readPort(fetchByte());
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addCycles(11);
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tick(11);
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break;
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case 4: // EX (SP),HL
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xhtl();
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addCycles(19);
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tick(19);
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break;
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case 5: // EX DE,HL
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std::swap(DE(), HL());
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addCycles(4);
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tick(4);
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break;
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case 6: // DI
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di();
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addCycles(4);
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tick(4);
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break;
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case 7: // EI
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ei();
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addCycles(4);
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tick(4);
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break;
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}
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break;
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case 4: // Conditional call: CALL cc[y], nn
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if (callConditionalFlag(y))
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addCycles(7);
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addCycles(10);
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tick(7);
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tick(10);
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break;
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case 5: // PUSH & various ops
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switch (q) {
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case 0: // PUSH rp2[p]
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pushWord(RP2(p));
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addCycles(11);
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tick(11);
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break;
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case 1:
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switch (p) {
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case 0: // CALL nn
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call(fetchWord());
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addCycles(17);
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tick(17);
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break;
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}
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break;
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@ -612,11 +612,11 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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default:
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UNREACHABLE;
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}
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addCycles(7);
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tick(7);
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break;
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case 7: // Restart: RST y * 8
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restart(y << 3);
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addCycles(11);
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tick(11);
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break;
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default:
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UNREACHABLE;
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@ -30,7 +30,7 @@ void EightBit::GameBoy::LR35902::handleRESET() {
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IntelProcessor::handleRESET();
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di();
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SP() = Mask16 - 1;
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addCycles(4);
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tick(4);
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}
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void EightBit::GameBoy::LR35902::handleINT() {
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@ -38,7 +38,7 @@ void EightBit::GameBoy::LR35902::handleINT() {
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raise(HALT());
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di();
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restart(BUS().DATA());
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addCycles(4);
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tick(4);
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}
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void EightBit::GameBoy::LR35902::di() {
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@ -393,29 +393,29 @@ void EightBit::GameBoy::LR35902::executeCB(const int x, const int y, const int z
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default:
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UNREACHABLE;
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}
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addCycles(2);
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tick(2);
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R(z, operand);
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adjustZero<LR35902>(F(), operand);
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if (UNLIKELY(z == 6))
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addCycles(2);
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tick(2);
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break;
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} case 1: // BIT y, r[z]
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bit(y, R(z));
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addCycles(2);
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tick(2);
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if (UNLIKELY(z == 6))
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addCycles(2);
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tick(2);
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break;
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case 2: // RES y, r[z]
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R(z, res(y, R(z)));
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addCycles(2);
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tick(2);
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if (UNLIKELY(z == 6))
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addCycles(2);
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tick(2);
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break;
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case 3: // SET y, r[z]
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R(z, set(y, R(z)));
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addCycles(2);
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tick(2);
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if (UNLIKELY(z == 6))
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addCycles(2);
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tick(2);
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break;
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default:
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UNREACHABLE;
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@ -429,28 +429,28 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
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case 0: // Relative jumps and assorted ops
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switch (y) {
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case 0: // NOP
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addCycle();
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tick();
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break;
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case 1: // GB: LD (nn),SP
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BUS().ADDRESS() = fetchWord();
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setWord(SP());
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addCycles(5);
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tick(5);
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break;
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case 2: // GB: STOP
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stop();
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addCycle();
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tick();
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break;
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case 3: // JR d
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jr(fetchByte());
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addCycles(4);
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tick(4);
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break;
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case 4: // JR cc,d
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case 5:
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case 6:
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case 7:
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if (jrConditionalFlag(y - 4))
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addCycle();
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addCycles(2);
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tick();
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tick(2);
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break;
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default:
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UNREACHABLE;
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@ -460,11 +460,11 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
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switch (q) {
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case 0: // LD rp,nn
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RP(p) = fetchWord();
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addCycles(3);
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tick(3);
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break;
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case 1: // ADD HL,rp
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add(HL(), RP(p));
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addCycles(2);
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tick(2);
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break;
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default:
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UNREACHABLE;
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@ -476,19 +476,19 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
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switch (p) {
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case 0: // LD (BC),A
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BUS().write(BC(), A());
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addCycles(2);
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tick(2);
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break;
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case 1: // LD (DE),A
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BUS().write(DE(), A());
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addCycles(2);
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tick(2);
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break;
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case 2: // GB: LDI (HL),A
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BUS().write(HL()++, A());
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addCycles(2);
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tick(2);
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break;
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case 3: // GB: LDD (HL),A
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BUS().write(HL()--, A());
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addCycles(2);
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tick(2);
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break;
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default:
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UNREACHABLE;
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@ -498,19 +498,19 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
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switch (p) {
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case 0: // LD A,(BC)
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A() = BUS().read(BC());
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addCycles(2);
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tick(2);
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break;
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case 1: // LD A,(DE)
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A() = BUS().read(DE());
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addCycles(2);
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tick(2);
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break;
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case 2: // GB: LDI A,(HL)
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A() = BUS().read(HL()++);
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addCycles(2);
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tick(2);
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break;
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case 3: // GB: LDD A,(HL)
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A() = BUS().read(HL()--);
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addCycles(2);
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tick(2);
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break;
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default:
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UNREACHABLE;
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@ -531,27 +531,27 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
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default:
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UNREACHABLE;
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}
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addCycles(2);
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tick(2);
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break;
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case 4: { // 8-bit INC
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auto operand = R(y);
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increment(operand);
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R(y, operand);
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addCycle();
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tick();
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if (UNLIKELY(y == 6))
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addCycles(2);
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tick(2);
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break;
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} case 5: { // 8-bit DEC
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auto operand = R(y);
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decrement(operand);
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R(y, operand);
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addCycle();
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tick();
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if (UNLIKELY(y == 6))
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addCycles(2);
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tick(2);
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break;
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} case 6: // 8-bit load immediate
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R(y, fetchByte()); // LD r,n
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addCycles(2);
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tick(2);
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y) {
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@ -582,7 +582,7 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
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default:
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UNREACHABLE;
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}
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addCycle();
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tick();
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break;
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default:
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UNREACHABLE;
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@ -594,9 +594,9 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
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} else {
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R(y, R(z));
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if (UNLIKELY((y == 6) || (z == 6))) // M operations
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addCycle();
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tick();
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}
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addCycle();
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tick();
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break;
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case 2: // Operate on accumulator and register/memory location
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switch (y) {
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@ -627,9 +627,9 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
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default:
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UNREACHABLE;
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}
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addCycle();
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tick();
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if (UNLIKELY(z == 6))
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addCycle();
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tick();
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break;
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case 3:
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switch (z) {
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@ -640,12 +640,12 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
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case 2:
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case 3:
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if (returnConditionalFlag(y))
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addCycles(3);
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addCycles(2);
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tick(3);
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tick(2);
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break;
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case 4: // GB: LD (FF00 + n),A
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BUS().write(IoRegisters::BASE + fetchByte(), A());
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addCycles(3);
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tick(3);
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break;
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case 5: { // GB: ADD SP,dd
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const auto before = SP().word;
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@ -657,11 +657,11 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
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setFlag(F(), CF, carried & Bit8);
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setFlag(F(), HC, carried & Bit4);
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}
|
||||
addCycles(4);
|
||||
tick(4);
|
||||
break;
|
||||
case 6: // GB: LD A,(FF00 + n)
|
||||
A() = BUS().read(IoRegisters::BASE + fetchByte());
|
||||
addCycles(3);
|
||||
tick(3);
|
||||
break;
|
||||
case 7: { // GB: LD HL,SP + dd
|
||||
const auto before = SP().word;
|
||||
@ -673,7 +673,7 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
setFlag(F(), CF, carried & Bit8);
|
||||
setFlag(F(), HC, carried & Bit4);
|
||||
}
|
||||
addCycles(3);
|
||||
tick(3);
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE;
|
||||
@ -683,25 +683,25 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
switch (q) {
|
||||
case 0: // POP rp2[p]
|
||||
RP2(p) = popWord();
|
||||
addCycles(3);
|
||||
tick(3);
|
||||
break;
|
||||
case 1:
|
||||
switch (p) {
|
||||
case 0: // RET
|
||||
ret();
|
||||
addCycles(4);
|
||||
tick(4);
|
||||
break;
|
||||
case 1: // GB: RETI
|
||||
reti();
|
||||
addCycles(4);
|
||||
tick(4);
|
||||
break;
|
||||
case 2: // JP HL
|
||||
jump(HL());
|
||||
addCycle();
|
||||
tick();
|
||||
break;
|
||||
case 3: // LD SP,HL
|
||||
SP() = HL();
|
||||
addCycles(2);
|
||||
tick(2);
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE;
|
||||
@ -718,25 +718,25 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
case 2:
|
||||
case 3:
|
||||
jumpConditionalFlag(y);
|
||||
addCycles(3);
|
||||
tick(3);
|
||||
break;
|
||||
case 4: // GB: LD (FF00 + C),A
|
||||
BUS().write(IoRegisters::BASE + C(), A());
|
||||
addCycles(2);
|
||||
tick(2);
|
||||
break;
|
||||
case 5: // GB: LD (nn),A
|
||||
BUS().ADDRESS() = MEMPTR() = fetchWord();
|
||||
BUS().write(A());
|
||||
addCycles(4);
|
||||
tick(4);
|
||||
break;
|
||||
case 6: // GB: LD A,(FF00 + C)
|
||||
A() = BUS().read(IoRegisters::BASE + C());
|
||||
addCycles(2);
|
||||
tick(2);
|
||||
break;
|
||||
case 7: // GB: LD A,(nn)
|
||||
BUS().ADDRESS() = MEMPTR() = fetchWord();
|
||||
A() = BUS().read();
|
||||
addCycles(4);
|
||||
tick(4);
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE;
|
||||
@ -746,7 +746,7 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
switch (y) {
|
||||
case 0: // JP nn
|
||||
jump(MEMPTR() = fetchWord());
|
||||
addCycles(4);
|
||||
tick(4);
|
||||
break;
|
||||
case 1: // CB prefix
|
||||
m_prefixCB = true;
|
||||
@ -754,30 +754,30 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
break;
|
||||
case 6: // DI
|
||||
di();
|
||||
addCycle();
|
||||
tick();
|
||||
break;
|
||||
case 7: // EI
|
||||
ei();
|
||||
addCycle();
|
||||
tick();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 4: // Conditional call: CALL cc[y], nn
|
||||
if (callConditionalFlag(y))
|
||||
addCycles(3);
|
||||
addCycles(3);
|
||||
tick(3);
|
||||
tick(3);
|
||||
break;
|
||||
case 5: // PUSH & various ops
|
||||
switch (q) {
|
||||
case 0: // PUSH rp2[p]
|
||||
pushWord(RP2(p));
|
||||
addCycles(4);
|
||||
tick(4);
|
||||
break;
|
||||
case 1:
|
||||
switch (p) {
|
||||
case 0: // CALL nn
|
||||
call(MEMPTR() = fetchWord());
|
||||
addCycles(6);
|
||||
tick(6);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -814,11 +814,11 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
addCycles(2);
|
||||
tick(2);
|
||||
break;
|
||||
case 7: // Restart: RST y * 8
|
||||
restart(y << 3);
|
||||
addCycles(4);
|
||||
tick(4);
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE;
|
||||
|
||||
@ -23,7 +23,7 @@ int EightBit::MOS6502::step() {
|
||||
resetCycles();
|
||||
ExecutingInstruction.fire(*this);
|
||||
if (LIKELY(powered())) {
|
||||
addCycle();
|
||||
tick();
|
||||
if (UNLIKELY(lowered(SO())))
|
||||
handleSO();
|
||||
if (LIKELY(raised(RDY()))) {
|
||||
@ -91,12 +91,12 @@ void EightBit::MOS6502::interrupt() {
|
||||
//
|
||||
|
||||
void EightBit::MOS6502::busWrite() {
|
||||
addCycle();
|
||||
tick();
|
||||
Processor::busWrite();
|
||||
}
|
||||
|
||||
uint8_t EightBit::MOS6502::busRead() {
|
||||
addCycle();
|
||||
tick();
|
||||
return Processor::busRead();
|
||||
}
|
||||
|
||||
@ -396,7 +396,7 @@ uint8_t EightBit::MOS6502::pop() {
|
||||
}
|
||||
|
||||
void EightBit::MOS6502::dummyPush(const uint8_t value) {
|
||||
addCycle();
|
||||
tick();
|
||||
BUS().DATA() = value;
|
||||
BUS().ADDRESS() = register16_t(S()--, 1);
|
||||
}
|
||||
|
||||
@ -295,7 +295,7 @@ namespace EightBit {
|
||||
|
||||
void branchLong(const int condition) {
|
||||
if (branch(Address_relative_word(), condition))
|
||||
addCycle();
|
||||
tick();
|
||||
}
|
||||
|
||||
// Miscellaneous
|
||||
|
||||
@ -51,7 +51,7 @@ void EightBit::mc6809::handleRESET() {
|
||||
setFlag(CC(), IF); // Disable IRQ
|
||||
setFlag(CC(), FF); // Disable FIRQ
|
||||
jump(getWordPaged(0xff, RESETvector));
|
||||
addCycles(10);
|
||||
tick(10);
|
||||
}
|
||||
|
||||
void EightBit::mc6809::handleNMI() {
|
||||
@ -62,7 +62,7 @@ void EightBit::mc6809::handleNMI() {
|
||||
setFlag(CC(), IF); // Disable IRQ
|
||||
setFlag(CC(), FF); // Disable FIRQ
|
||||
jump(getWordPaged(0xff, NMIvector));
|
||||
addCycles(12);
|
||||
tick(12);
|
||||
}
|
||||
|
||||
void EightBit::mc6809::handleIRQ() {
|
||||
@ -72,7 +72,7 @@ void EightBit::mc6809::handleIRQ() {
|
||||
saveEntireRegisterState();
|
||||
setFlag(CC(), IF); // Disable IRQ
|
||||
jump(getWordPaged(0xff, IRQvector));
|
||||
addCycles(12);
|
||||
tick(12);
|
||||
}
|
||||
|
||||
void EightBit::mc6809::handleFIRQ() {
|
||||
@ -83,7 +83,7 @@ void EightBit::mc6809::handleFIRQ() {
|
||||
setFlag(CC(), IF); // Disable IRQ
|
||||
setFlag(CC(), FF); // Disable FIRQ
|
||||
jump(getWordPaged(0xff, FIRQvector));
|
||||
addCycles(12);
|
||||
tick(12);
|
||||
}
|
||||
|
||||
//
|
||||
@ -116,359 +116,359 @@ void EightBit::mc6809::executeUnprefixed() {
|
||||
case 0x11: m_prefix11 = true; Processor::execute(fetchByte()); break;
|
||||
|
||||
// ABX
|
||||
case 0x3a: addCycles(3); X() += B(); break; // ABX (inherent)
|
||||
case 0x3a: tick(3); X() += B(); break; // ABX (inherent)
|
||||
|
||||
// ADC
|
||||
case 0x89: addCycles(2); A() = adc(A(), AM_immediate_byte()); break; // ADC (ADCA immediate)
|
||||
case 0x99: addCycles(4); A() = adc(A(), AM_direct_byte()); break; // ADC (ADCA direct)
|
||||
case 0xa9: addCycles(4); A() = adc(A(), AM_indexed_byte()); break; // ADC (ADCA indexed)
|
||||
case 0xb9: addCycles(4); A() = adc(A(), AM_extended_byte()); break; // ADC (ADCA extended)
|
||||
case 0x89: tick(2); A() = adc(A(), AM_immediate_byte()); break; // ADC (ADCA immediate)
|
||||
case 0x99: tick(4); A() = adc(A(), AM_direct_byte()); break; // ADC (ADCA direct)
|
||||
case 0xa9: tick(4); A() = adc(A(), AM_indexed_byte()); break; // ADC (ADCA indexed)
|
||||
case 0xb9: tick(4); A() = adc(A(), AM_extended_byte()); break; // ADC (ADCA extended)
|
||||
|
||||
case 0xc9: addCycles(2); B() = adc(B(), AM_immediate_byte()); break; // ADC (ADCB immediate)
|
||||
case 0xd9: addCycles(4); B() = adc(B(), AM_direct_byte()); break; // ADC (ADCB direct)
|
||||
case 0xe9: addCycles(4); B() = adc(B(), AM_indexed_byte()); break; // ADC (ADCB indexed)
|
||||
case 0xf9: addCycles(4); B() = adc(B(), AM_extended_byte()); break; // ADC (ADCB extended)
|
||||
case 0xc9: tick(2); B() = adc(B(), AM_immediate_byte()); break; // ADC (ADCB immediate)
|
||||
case 0xd9: tick(4); B() = adc(B(), AM_direct_byte()); break; // ADC (ADCB direct)
|
||||
case 0xe9: tick(4); B() = adc(B(), AM_indexed_byte()); break; // ADC (ADCB indexed)
|
||||
case 0xf9: tick(4); B() = adc(B(), AM_extended_byte()); break; // ADC (ADCB extended)
|
||||
|
||||
// ADD
|
||||
case 0x8b: addCycles(2); A() = add(A(), AM_immediate_byte()); break; // ADD (ADDA immediate)
|
||||
case 0x9b: addCycles(4); A() = add(A(), AM_direct_byte()); break; // ADD (ADDA direct)
|
||||
case 0xab: addCycles(4); A() = add(A(), AM_indexed_byte()); break; // ADD (ADDA indexed)
|
||||
case 0xbb: addCycles(5); A() = add(A(), AM_extended_byte()); break; // ADD (ADDA extended)
|
||||
case 0x8b: tick(2); A() = add(A(), AM_immediate_byte()); break; // ADD (ADDA immediate)
|
||||
case 0x9b: tick(4); A() = add(A(), AM_direct_byte()); break; // ADD (ADDA direct)
|
||||
case 0xab: tick(4); A() = add(A(), AM_indexed_byte()); break; // ADD (ADDA indexed)
|
||||
case 0xbb: tick(5); A() = add(A(), AM_extended_byte()); break; // ADD (ADDA extended)
|
||||
|
||||
case 0xcb: addCycles(2); B() = add(B(), AM_immediate_byte()); break; // ADD (ADDB immediate)
|
||||
case 0xdb: addCycles(4); B() = add(B(), AM_direct_byte()); break; // ADD (ADDB direct)
|
||||
case 0xeb: addCycles(4); B() = add(B(), AM_indexed_byte()); break; // ADD (ADDB indexed)
|
||||
case 0xfb: addCycles(5); B() = add(B(), AM_extended_byte()); break; // ADD (ADDB extended)
|
||||
case 0xcb: tick(2); B() = add(B(), AM_immediate_byte()); break; // ADD (ADDB immediate)
|
||||
case 0xdb: tick(4); B() = add(B(), AM_direct_byte()); break; // ADD (ADDB direct)
|
||||
case 0xeb: tick(4); B() = add(B(), AM_indexed_byte()); break; // ADD (ADDB indexed)
|
||||
case 0xfb: tick(5); B() = add(B(), AM_extended_byte()); break; // ADD (ADDB extended)
|
||||
|
||||
case 0xc3: addCycles(4); D() = add(D(), AM_immediate_word()); break; // ADD (ADDD immediate)
|
||||
case 0xd3: addCycles(6); D() = add(D(), AM_direct_word()); break; // ADD (ADDD direct)
|
||||
case 0xe3: addCycles(6); D() = add(D(), AM_indexed_word()); break; // ADD (ADDD indexed)
|
||||
case 0xf3: addCycles(7); D() = add(D(), AM_extended_word()); break; // ADD (ADDD extended)
|
||||
case 0xc3: tick(4); D() = add(D(), AM_immediate_word()); break; // ADD (ADDD immediate)
|
||||
case 0xd3: tick(6); D() = add(D(), AM_direct_word()); break; // ADD (ADDD direct)
|
||||
case 0xe3: tick(6); D() = add(D(), AM_indexed_word()); break; // ADD (ADDD indexed)
|
||||
case 0xf3: tick(7); D() = add(D(), AM_extended_word()); break; // ADD (ADDD extended)
|
||||
|
||||
// AND
|
||||
case 0x84: addCycles(2); A() = andr(A(), AM_immediate_byte()); break; // AND (ANDA immediate)
|
||||
case 0x94: addCycles(4); A() = andr(A(), AM_direct_byte()); break; // AND (ANDA direct)
|
||||
case 0xa4: addCycles(4); A() = andr(A(), AM_indexed_byte()); break; // AND (ANDA indexed)
|
||||
case 0xb4: addCycles(5); A() = andr(A(), AM_extended_byte()); break; // AND (ANDA extended)
|
||||
case 0x84: tick(2); A() = andr(A(), AM_immediate_byte()); break; // AND (ANDA immediate)
|
||||
case 0x94: tick(4); A() = andr(A(), AM_direct_byte()); break; // AND (ANDA direct)
|
||||
case 0xa4: tick(4); A() = andr(A(), AM_indexed_byte()); break; // AND (ANDA indexed)
|
||||
case 0xb4: tick(5); A() = andr(A(), AM_extended_byte()); break; // AND (ANDA extended)
|
||||
|
||||
case 0xc4: addCycles(2); B() = andr(B(), AM_immediate_byte()); break; // AND (ANDB immediate)
|
||||
case 0xd4: addCycles(4); B() = andr(B(), AM_direct_byte()); break; // AND (ANDB direct)
|
||||
case 0xe4: addCycles(4); B() = andr(B(), AM_indexed_byte()); break; // AND (ANDB indexed)
|
||||
case 0xf4: addCycles(5); B() = andr(B(), AM_extended_byte()); break; // AND (ANDB extended)
|
||||
case 0xc4: tick(2); B() = andr(B(), AM_immediate_byte()); break; // AND (ANDB immediate)
|
||||
case 0xd4: tick(4); B() = andr(B(), AM_direct_byte()); break; // AND (ANDB direct)
|
||||
case 0xe4: tick(4); B() = andr(B(), AM_indexed_byte()); break; // AND (ANDB indexed)
|
||||
case 0xf4: tick(5); B() = andr(B(), AM_extended_byte()); break; // AND (ANDB extended)
|
||||
|
||||
case 0x1c: addCycles(3); CC() &= AM_immediate_byte(); break; // AND (ANDCC immediate)
|
||||
case 0x1c: tick(3); CC() &= AM_immediate_byte(); break; // AND (ANDCC immediate)
|
||||
|
||||
// ASL/LSL
|
||||
case 0x08: addCycles(6); BUS().write(asl(AM_direct_byte())); break; // ASL (direct)
|
||||
case 0x48: addCycles(2); A() = asl(A()); break; // ASL (ASLA inherent)
|
||||
case 0x58: addCycles(2); B() = asl(B()); break; // ASL (ASLB inherent)
|
||||
case 0x68: addCycles(6); BUS().write(asl(AM_indexed_byte())); break; // ASL (indexed)
|
||||
case 0x78: addCycles(7); BUS().write(asl(AM_extended_byte())); break; // ASL (extended)
|
||||
case 0x08: tick(6); BUS().write(asl(AM_direct_byte())); break; // ASL (direct)
|
||||
case 0x48: tick(2); A() = asl(A()); break; // ASL (ASLA inherent)
|
||||
case 0x58: tick(2); B() = asl(B()); break; // ASL (ASLB inherent)
|
||||
case 0x68: tick(6); BUS().write(asl(AM_indexed_byte())); break; // ASL (indexed)
|
||||
case 0x78: tick(7); BUS().write(asl(AM_extended_byte())); break; // ASL (extended)
|
||||
|
||||
// ASR
|
||||
case 0x07: addCycles(6); BUS().write(asr(AM_direct_byte())); break; // ASR (direct)
|
||||
case 0x47: addCycles(2); A() = asr(A()); break; // ASR (ASRA inherent)
|
||||
case 0x57: addCycles(2); B() = asr(B()); break; // ASR (ASRB inherent)
|
||||
case 0x67: addCycles(6); BUS().write(asr(AM_indexed_byte())); break; // ASR (indexed)
|
||||
case 0x77: addCycles(7); BUS().write(asr(AM_extended_byte())); break; // ASR (extended)
|
||||
case 0x07: tick(6); BUS().write(asr(AM_direct_byte())); break; // ASR (direct)
|
||||
case 0x47: tick(2); A() = asr(A()); break; // ASR (ASRA inherent)
|
||||
case 0x57: tick(2); B() = asr(B()); break; // ASR (ASRB inherent)
|
||||
case 0x67: tick(6); BUS().write(asr(AM_indexed_byte())); break; // ASR (indexed)
|
||||
case 0x77: tick(7); BUS().write(asr(AM_extended_byte())); break; // ASR (extended)
|
||||
|
||||
// BIT
|
||||
case 0x85: addCycles(2); bit(A(), AM_immediate_byte()); break; // BIT (BITA immediate)
|
||||
case 0x95: addCycles(4); bit(A(), AM_direct_byte()); break; // BIT (BITA direct)
|
||||
case 0xa5: addCycles(4); bit(A(), AM_indexed_byte()); break; // BIT (BITA indexed)
|
||||
case 0xb5: addCycles(5); bit(A(), AM_extended_byte()); break; // BIT (BITA extended)
|
||||
case 0x85: tick(2); bit(A(), AM_immediate_byte()); break; // BIT (BITA immediate)
|
||||
case 0x95: tick(4); bit(A(), AM_direct_byte()); break; // BIT (BITA direct)
|
||||
case 0xa5: tick(4); bit(A(), AM_indexed_byte()); break; // BIT (BITA indexed)
|
||||
case 0xb5: tick(5); bit(A(), AM_extended_byte()); break; // BIT (BITA extended)
|
||||
|
||||
case 0xc5: addCycles(2); bit(B(), AM_immediate_byte()); break; // BIT (BITB immediate)
|
||||
case 0xd5: addCycles(4); bit(B(), AM_direct_byte()); break; // BIT (BITB direct)
|
||||
case 0xe5: addCycles(4); bit(B(), AM_indexed_byte()); break; // BIT (BITB indexed)
|
||||
case 0xf5: addCycles(5); bit(B(), AM_extended_byte()); break; // BIT (BITB extended)
|
||||
case 0xc5: tick(2); bit(B(), AM_immediate_byte()); break; // BIT (BITB immediate)
|
||||
case 0xd5: tick(4); bit(B(), AM_direct_byte()); break; // BIT (BITB direct)
|
||||
case 0xe5: tick(4); bit(B(), AM_indexed_byte()); break; // BIT (BITB indexed)
|
||||
case 0xf5: tick(5); bit(B(), AM_extended_byte()); break; // BIT (BITB extended)
|
||||
|
||||
// CLR
|
||||
case 0x0f: addCycles(6); BUS().write(Address_direct(), clr()); break; // CLR (direct)
|
||||
case 0x4f: addCycles(2); A() = clr(); break; // CLR (CLRA implied)
|
||||
case 0x5f: addCycles(2); B() = clr(); break; // CLR (CLRB implied)
|
||||
case 0x6f: addCycles(6); BUS().write(Address_indexed(), clr()); break; // CLR (indexed)
|
||||
case 0x7f: addCycles(7); BUS().write(Address_extended(), clr()); break; // CLR (extended)
|
||||
case 0x0f: tick(6); BUS().write(Address_direct(), clr()); break; // CLR (direct)
|
||||
case 0x4f: tick(2); A() = clr(); break; // CLR (CLRA implied)
|
||||
case 0x5f: tick(2); B() = clr(); break; // CLR (CLRB implied)
|
||||
case 0x6f: tick(6); BUS().write(Address_indexed(), clr()); break; // CLR (indexed)
|
||||
case 0x7f: tick(7); BUS().write(Address_extended(), clr()); break; // CLR (extended)
|
||||
|
||||
// CMP
|
||||
|
||||
// CMPA
|
||||
case 0x81: addCycles(2); cmp(A(), AM_immediate_byte()); break; // CMP (CMPA, immediate)
|
||||
case 0x91: addCycles(4); cmp(A(), AM_direct_byte()); break; // CMP (CMPA, direct)
|
||||
case 0xa1: addCycles(4); cmp(A(), AM_indexed_byte()); break; // CMP (CMPA, indexed)
|
||||
case 0xb1: addCycles(5); cmp(A(), AM_extended_byte()); break; // CMP (CMPA, extended)
|
||||
case 0x81: tick(2); cmp(A(), AM_immediate_byte()); break; // CMP (CMPA, immediate)
|
||||
case 0x91: tick(4); cmp(A(), AM_direct_byte()); break; // CMP (CMPA, direct)
|
||||
case 0xa1: tick(4); cmp(A(), AM_indexed_byte()); break; // CMP (CMPA, indexed)
|
||||
case 0xb1: tick(5); cmp(A(), AM_extended_byte()); break; // CMP (CMPA, extended)
|
||||
|
||||
// CMPB
|
||||
case 0xc1: addCycles(2); cmp(B(), AM_immediate_byte()); break; // CMP (CMPB, immediate)
|
||||
case 0xd1: addCycles(4); cmp(B(), AM_direct_byte()); break; // CMP (CMPB, direct)
|
||||
case 0xe1: addCycles(4); cmp(B(), AM_indexed_byte()); break; // CMP (CMPB, indexed)
|
||||
case 0xf1: addCycles(5); cmp(B(), AM_extended_byte()); break; // CMP (CMPB, extended)
|
||||
case 0xc1: tick(2); cmp(B(), AM_immediate_byte()); break; // CMP (CMPB, immediate)
|
||||
case 0xd1: tick(4); cmp(B(), AM_direct_byte()); break; // CMP (CMPB, direct)
|
||||
case 0xe1: tick(4); cmp(B(), AM_indexed_byte()); break; // CMP (CMPB, indexed)
|
||||
case 0xf1: tick(5); cmp(B(), AM_extended_byte()); break; // CMP (CMPB, extended)
|
||||
|
||||
// CMPX
|
||||
case 0x8c: addCycles(4); cmp(X(), AM_immediate_word()); break; // CMP (CMPX, immediate)
|
||||
case 0x9c: addCycles(6); cmp(X(), AM_direct_word()); break; // CMP (CMPX, direct)
|
||||
case 0xac: addCycles(6); cmp(X(), AM_indexed_word()); break; // CMP (CMPX, indexed)
|
||||
case 0xbc: addCycles(7); cmp(X(), AM_extended_word()); break; // CMP (CMPX, extended)
|
||||
case 0x8c: tick(4); cmp(X(), AM_immediate_word()); break; // CMP (CMPX, immediate)
|
||||
case 0x9c: tick(6); cmp(X(), AM_direct_word()); break; // CMP (CMPX, direct)
|
||||
case 0xac: tick(6); cmp(X(), AM_indexed_word()); break; // CMP (CMPX, indexed)
|
||||
case 0xbc: tick(7); cmp(X(), AM_extended_word()); break; // CMP (CMPX, extended)
|
||||
|
||||
// COM
|
||||
case 0x03: addCycles(6); BUS().write(com(AM_direct_byte())); break; // COM (direct)
|
||||
case 0x43: addCycles(2); A() = com(A()); break; // COM (COMA inherent)
|
||||
case 0x53: addCycles(2); B() = com(B()); break; // COM (COMB inherent)
|
||||
case 0x63: addCycles(6); BUS().write(com(AM_indexed_byte())); break; // COM (indexed)
|
||||
case 0x73: addCycles(7); BUS().write(com(AM_extended_byte())); break; // COM (extended)
|
||||
case 0x03: tick(6); BUS().write(com(AM_direct_byte())); break; // COM (direct)
|
||||
case 0x43: tick(2); A() = com(A()); break; // COM (COMA inherent)
|
||||
case 0x53: tick(2); B() = com(B()); break; // COM (COMB inherent)
|
||||
case 0x63: tick(6); BUS().write(com(AM_indexed_byte())); break; // COM (indexed)
|
||||
case 0x73: tick(7); BUS().write(com(AM_extended_byte())); break; // COM (extended)
|
||||
|
||||
// CWAI
|
||||
case 0x3c: addCycles(11); cwai(AM_direct_byte()); break; // CWAI (direct)
|
||||
case 0x3c: tick(11); cwai(AM_direct_byte()); break; // CWAI (direct)
|
||||
|
||||
// DAA
|
||||
case 0x19: addCycles(2); A() = da(A()); break; // DAA (inherent)
|
||||
case 0x19: tick(2); A() = da(A()); break; // DAA (inherent)
|
||||
|
||||
// DEC
|
||||
case 0x0a: addCycles(6); BUS().write(dec(AM_direct_byte())); break; // DEC (direct)
|
||||
case 0x4a: addCycles(2); A() = dec(A()); break; // DEC (DECA inherent)
|
||||
case 0x5a: addCycles(2); B() = dec(B()); break; // DEC (DECB inherent)
|
||||
case 0x6a: addCycles(6); BUS().write(dec(AM_indexed_byte())); break; // DEC (indexed)
|
||||
case 0x7a: addCycles(7); BUS().write(dec(AM_extended_byte())); break; // DEC (extended)
|
||||
case 0x0a: tick(6); BUS().write(dec(AM_direct_byte())); break; // DEC (direct)
|
||||
case 0x4a: tick(2); A() = dec(A()); break; // DEC (DECA inherent)
|
||||
case 0x5a: tick(2); B() = dec(B()); break; // DEC (DECB inherent)
|
||||
case 0x6a: tick(6); BUS().write(dec(AM_indexed_byte())); break; // DEC (indexed)
|
||||
case 0x7a: tick(7); BUS().write(dec(AM_extended_byte())); break; // DEC (extended)
|
||||
|
||||
// EOR
|
||||
|
||||
// EORA
|
||||
case 0x88: addCycles(2); A() = eorr(A(), AM_immediate_byte()); break; // EOR (EORA immediate)
|
||||
case 0x98: addCycles(4); A() = eorr(A(), AM_direct_byte()); break; // EOR (EORA direct)
|
||||
case 0xa8: addCycles(4); A() = eorr(A(), AM_indexed_byte()); break; // EOR (EORA indexed)
|
||||
case 0xb8: addCycles(5); A() = eorr(A(), AM_extended_byte()); break; // EOR (EORA extended)
|
||||
case 0x88: tick(2); A() = eorr(A(), AM_immediate_byte()); break; // EOR (EORA immediate)
|
||||
case 0x98: tick(4); A() = eorr(A(), AM_direct_byte()); break; // EOR (EORA direct)
|
||||
case 0xa8: tick(4); A() = eorr(A(), AM_indexed_byte()); break; // EOR (EORA indexed)
|
||||
case 0xb8: tick(5); A() = eorr(A(), AM_extended_byte()); break; // EOR (EORA extended)
|
||||
|
||||
// EORB
|
||||
case 0xc8: addCycles(2); B() = eorr(B(), AM_immediate_byte()); break; // EOR (EORB immediate)
|
||||
case 0xd8: addCycles(4); B() = eorr(B(), AM_direct_byte()); break; // EOR (EORB direct)
|
||||
case 0xe8: addCycles(4); B() = eorr(B(), AM_indexed_byte()); break; // EOR (EORB indexed)
|
||||
case 0xf8: addCycles(5); B() = eorr(B(), AM_extended_byte()); break; // EOR (EORB extended)
|
||||
case 0xc8: tick(2); B() = eorr(B(), AM_immediate_byte()); break; // EOR (EORB immediate)
|
||||
case 0xd8: tick(4); B() = eorr(B(), AM_direct_byte()); break; // EOR (EORB direct)
|
||||
case 0xe8: tick(4); B() = eorr(B(), AM_indexed_byte()); break; // EOR (EORB indexed)
|
||||
case 0xf8: tick(5); B() = eorr(B(), AM_extended_byte()); break; // EOR (EORB extended)
|
||||
|
||||
// EXG
|
||||
case 0x1e: addCycles(8); exg(AM_immediate_byte()); break; // EXG (R1,R2 immediate)
|
||||
case 0x1e: tick(8); exg(AM_immediate_byte()); break; // EXG (R1,R2 immediate)
|
||||
|
||||
// INC
|
||||
case 0x0c: addCycles(6); BUS().write(inc(AM_direct_byte())); break; // INC (direct)
|
||||
case 0x4c: addCycles(2); A() = inc(A()); break; // INC (INCA inherent)
|
||||
case 0x5c: addCycles(2); B() = inc(B()); break; // INC (INCB inherent)
|
||||
case 0x6c: addCycles(6); BUS().write(inc(AM_indexed_byte())); break; // INC (indexed)
|
||||
case 0x7c: addCycles(7); BUS().write(inc(AM_extended_byte())); break; // INC (extended)
|
||||
case 0x0c: tick(6); BUS().write(inc(AM_direct_byte())); break; // INC (direct)
|
||||
case 0x4c: tick(2); A() = inc(A()); break; // INC (INCA inherent)
|
||||
case 0x5c: tick(2); B() = inc(B()); break; // INC (INCB inherent)
|
||||
case 0x6c: tick(6); BUS().write(inc(AM_indexed_byte())); break; // INC (indexed)
|
||||
case 0x7c: tick(7); BUS().write(inc(AM_extended_byte())); break; // INC (extended)
|
||||
|
||||
// JMP
|
||||
case 0x0e: addCycles(6); jump(Address_direct()); break; // JMP (direct)
|
||||
case 0x6e: addCycles(6); jump(Address_indexed()); break; // JMP (indexed)
|
||||
case 0x7e: addCycles(7); jump(Address_extended()); break; // JMP (extended)
|
||||
case 0x0e: tick(6); jump(Address_direct()); break; // JMP (direct)
|
||||
case 0x6e: tick(6); jump(Address_indexed()); break; // JMP (indexed)
|
||||
case 0x7e: tick(7); jump(Address_extended()); break; // JMP (extended)
|
||||
|
||||
// JSR
|
||||
case 0x9d: addCycles(6); jsr(Address_direct()); break; // JSR (direct)
|
||||
case 0xad: addCycles(6); jsr(Address_indexed()); break; // JSR (indexed)
|
||||
case 0xbd: addCycles(7); jsr(Address_extended()); break; // JSR (extended)
|
||||
case 0x9d: tick(6); jsr(Address_direct()); break; // JSR (direct)
|
||||
case 0xad: tick(6); jsr(Address_indexed()); break; // JSR (indexed)
|
||||
case 0xbd: tick(7); jsr(Address_extended()); break; // JSR (extended)
|
||||
|
||||
// LD
|
||||
|
||||
// LDA
|
||||
case 0x86: addCycles(2); A() = ld(AM_immediate_byte()); break; // LD (LDA immediate)
|
||||
case 0x96: addCycles(4); A() = ld(AM_direct_byte()); break; // LD (LDA direct)
|
||||
case 0xa6: addCycles(4); A() = ld(AM_indexed_byte()); break; // LD (LDA indexed)
|
||||
case 0xb6: addCycles(5); A() = ld(AM_extended_byte()); break; // LD (LDA extended)
|
||||
case 0x86: tick(2); A() = ld(AM_immediate_byte()); break; // LD (LDA immediate)
|
||||
case 0x96: tick(4); A() = ld(AM_direct_byte()); break; // LD (LDA direct)
|
||||
case 0xa6: tick(4); A() = ld(AM_indexed_byte()); break; // LD (LDA indexed)
|
||||
case 0xb6: tick(5); A() = ld(AM_extended_byte()); break; // LD (LDA extended)
|
||||
|
||||
// LDB
|
||||
case 0xc6: addCycles(2); B() = ld(AM_immediate_byte()); break; // LD (LDB immediate)
|
||||
case 0xd6: addCycles(4); B() = ld(AM_direct_byte()); break; // LD (LDB direct)
|
||||
case 0xe6: addCycles(4); B() = ld(AM_indexed_byte()); break; // LD (LDB indexed)
|
||||
case 0xf6: addCycles(5); B() = ld(AM_extended_byte()); break; // LD (LDB extended)
|
||||
case 0xc6: tick(2); B() = ld(AM_immediate_byte()); break; // LD (LDB immediate)
|
||||
case 0xd6: tick(4); B() = ld(AM_direct_byte()); break; // LD (LDB direct)
|
||||
case 0xe6: tick(4); B() = ld(AM_indexed_byte()); break; // LD (LDB indexed)
|
||||
case 0xf6: tick(5); B() = ld(AM_extended_byte()); break; // LD (LDB extended)
|
||||
|
||||
// LDD
|
||||
case 0xcc: addCycles(3); D() = ld(AM_immediate_word()); break; // LD (LDD immediate)
|
||||
case 0xdc: addCycles(5); D() = ld(AM_direct_word()); break; // LD (LDD direct)
|
||||
case 0xec: addCycles(5); D() = ld(AM_indexed_word()); break; // LD (LDD indexed)
|
||||
case 0xfc: addCycles(6); D() = ld(AM_extended_word()); break; // LD (LDD extended)
|
||||
case 0xcc: tick(3); D() = ld(AM_immediate_word()); break; // LD (LDD immediate)
|
||||
case 0xdc: tick(5); D() = ld(AM_direct_word()); break; // LD (LDD direct)
|
||||
case 0xec: tick(5); D() = ld(AM_indexed_word()); break; // LD (LDD indexed)
|
||||
case 0xfc: tick(6); D() = ld(AM_extended_word()); break; // LD (LDD extended)
|
||||
|
||||
// LDU
|
||||
case 0xce: addCycles(3); U() = ld(AM_immediate_word()); break; // LD (LDU immediate)
|
||||
case 0xde: addCycles(5); U() = ld(AM_direct_word()); break; // LD (LDU direct)
|
||||
case 0xee: addCycles(5); U() = ld(AM_indexed_word()); break; // LD (LDU indexed)
|
||||
case 0xfe: addCycles(6); U() = ld(AM_extended_word()); break; // LD (LDU extended)
|
||||
case 0xce: tick(3); U() = ld(AM_immediate_word()); break; // LD (LDU immediate)
|
||||
case 0xde: tick(5); U() = ld(AM_direct_word()); break; // LD (LDU direct)
|
||||
case 0xee: tick(5); U() = ld(AM_indexed_word()); break; // LD (LDU indexed)
|
||||
case 0xfe: tick(6); U() = ld(AM_extended_word()); break; // LD (LDU extended)
|
||||
|
||||
// LDX
|
||||
case 0x8e: addCycles(3); X() = ld(AM_immediate_word()); break; // LD (LDX immediate)
|
||||
case 0x9e: addCycles(5); X() = ld(AM_direct_word()); break; // LD (LDX direct)
|
||||
case 0xae: addCycles(5); X() = ld(AM_indexed_word()); break; // LD (LDX indexed)
|
||||
case 0xbe: addCycles(6); X() = ld(AM_extended_word()); break; // LD (LDX extended)
|
||||
case 0x8e: tick(3); X() = ld(AM_immediate_word()); break; // LD (LDX immediate)
|
||||
case 0x9e: tick(5); X() = ld(AM_direct_word()); break; // LD (LDX direct)
|
||||
case 0xae: tick(5); X() = ld(AM_indexed_word()); break; // LD (LDX indexed)
|
||||
case 0xbe: tick(6); X() = ld(AM_extended_word()); break; // LD (LDX extended)
|
||||
|
||||
// LEA
|
||||
case 0x30: addCycles(4); adjustZero(X() = Address_indexed()); break; // LEA (LEAX indexed)
|
||||
case 0x31: addCycles(4); adjustZero(Y() = Address_indexed()); break; // LEA (LEAY indexed)
|
||||
case 0x32: addCycles(4); S() = Address_indexed(); break; // LEA (LEAS indexed)
|
||||
case 0x33: addCycles(4); U() = Address_indexed(); break; // LEA (LEAU indexed)
|
||||
case 0x30: tick(4); adjustZero(X() = Address_indexed()); break; // LEA (LEAX indexed)
|
||||
case 0x31: tick(4); adjustZero(Y() = Address_indexed()); break; // LEA (LEAY indexed)
|
||||
case 0x32: tick(4); S() = Address_indexed(); break; // LEA (LEAS indexed)
|
||||
case 0x33: tick(4); U() = Address_indexed(); break; // LEA (LEAU indexed)
|
||||
|
||||
// LSR
|
||||
case 0x04: addCycles(6); BUS().write(lsr(AM_direct_byte())); break; // LSR (direct)
|
||||
case 0x44: addCycles(2); A() = lsr(A()); break; // LSR (LSRA inherent)
|
||||
case 0x54: addCycles(2); B() = lsr(B()); break; // LSR (LSRB inherent)
|
||||
case 0x64: addCycles(6); BUS().write(lsr(AM_indexed_byte())); break; // LSR (indexed)
|
||||
case 0x74: addCycles(7); BUS().write(lsr(AM_extended_byte())); break; // LSR (extended)
|
||||
case 0x04: tick(6); BUS().write(lsr(AM_direct_byte())); break; // LSR (direct)
|
||||
case 0x44: tick(2); A() = lsr(A()); break; // LSR (LSRA inherent)
|
||||
case 0x54: tick(2); B() = lsr(B()); break; // LSR (LSRB inherent)
|
||||
case 0x64: tick(6); BUS().write(lsr(AM_indexed_byte())); break; // LSR (indexed)
|
||||
case 0x74: tick(7); BUS().write(lsr(AM_extended_byte())); break; // LSR (extended)
|
||||
|
||||
// MUL
|
||||
case 0x3d: addCycles(11); D() = mul(A(), B()); break; // MUL (inherent)
|
||||
case 0x3d: tick(11); D() = mul(A(), B()); break; // MUL (inherent)
|
||||
|
||||
// NEG
|
||||
case 0x00: addCycles(6); BUS().write(neg(AM_direct_byte())); break; // NEG (direct)
|
||||
case 0x40: addCycles(2); A() = neg(A()); break; // NEG (NEGA, inherent)
|
||||
case 0x50: addCycles(2); B() = neg(B()); break; // NEG (NEGB, inherent)
|
||||
case 0x60: addCycles(6); BUS().write(neg(AM_indexed_byte())); break; // NEG (indexed)
|
||||
case 0x70: addCycles(7); BUS().write(neg(AM_extended_byte())); break; // NEG (extended)
|
||||
case 0x00: tick(6); BUS().write(neg(AM_direct_byte())); break; // NEG (direct)
|
||||
case 0x40: tick(2); A() = neg(A()); break; // NEG (NEGA, inherent)
|
||||
case 0x50: tick(2); B() = neg(B()); break; // NEG (NEGB, inherent)
|
||||
case 0x60: tick(6); BUS().write(neg(AM_indexed_byte())); break; // NEG (indexed)
|
||||
case 0x70: tick(7); BUS().write(neg(AM_extended_byte())); break; // NEG (extended)
|
||||
|
||||
// NOP
|
||||
case 0x12: addCycles(2); break; // NOP (inherent)
|
||||
case 0x12: tick(2); break; // NOP (inherent)
|
||||
|
||||
// OR
|
||||
|
||||
// ORA
|
||||
case 0x8a: addCycles(2); A() = orr(A(), AM_immediate_byte()); break; // OR (ORA immediate)
|
||||
case 0x9a: addCycles(4); A() = orr(A(), AM_direct_byte()); break; // OR (ORA direct)
|
||||
case 0xaa: addCycles(4); A() = orr(A(), AM_indexed_byte()); break; // OR (ORA indexed)
|
||||
case 0xba: addCycles(5); A() = orr(A(), AM_extended_byte()); break; // OR (ORA extended)
|
||||
case 0x8a: tick(2); A() = orr(A(), AM_immediate_byte()); break; // OR (ORA immediate)
|
||||
case 0x9a: tick(4); A() = orr(A(), AM_direct_byte()); break; // OR (ORA direct)
|
||||
case 0xaa: tick(4); A() = orr(A(), AM_indexed_byte()); break; // OR (ORA indexed)
|
||||
case 0xba: tick(5); A() = orr(A(), AM_extended_byte()); break; // OR (ORA extended)
|
||||
|
||||
// ORB
|
||||
case 0xca: addCycles(2); B() = orr(B(), AM_immediate_byte()); break; // OR (ORB immediate)
|
||||
case 0xda: addCycles(4); B() = orr(B(), AM_direct_byte()); break; // OR (ORB direct)
|
||||
case 0xea: addCycles(4); B() = orr(B(), AM_indexed_byte()); break; // OR (ORB indexed)
|
||||
case 0xfa: addCycles(5); B() = orr(B(), AM_extended_byte()); break; // OR (ORB extended)
|
||||
case 0xca: tick(2); B() = orr(B(), AM_immediate_byte()); break; // OR (ORB immediate)
|
||||
case 0xda: tick(4); B() = orr(B(), AM_direct_byte()); break; // OR (ORB direct)
|
||||
case 0xea: tick(4); B() = orr(B(), AM_indexed_byte()); break; // OR (ORB indexed)
|
||||
case 0xfa: tick(5); B() = orr(B(), AM_extended_byte()); break; // OR (ORB extended)
|
||||
|
||||
// ORCC
|
||||
case 0x1a: addCycles(3); CC() |= AM_immediate_byte(); break; // OR (ORCC immediate)
|
||||
case 0x1a: tick(3); CC() |= AM_immediate_byte(); break; // OR (ORCC immediate)
|
||||
|
||||
// PSH
|
||||
case 0x34: addCycles(5); psh(S(), AM_immediate_byte()); break; // PSH (PSHS immediate)
|
||||
case 0x36: addCycles(5); psh(U(), AM_immediate_byte()); break; // PSH (PSHU immediate)
|
||||
case 0x34: tick(5); psh(S(), AM_immediate_byte()); break; // PSH (PSHS immediate)
|
||||
case 0x36: tick(5); psh(U(), AM_immediate_byte()); break; // PSH (PSHU immediate)
|
||||
|
||||
// PUL
|
||||
case 0x35: addCycles(5); pul(S(), AM_immediate_byte()); break; // PUL (PULS immediate)
|
||||
case 0x37: addCycles(5); pul(U(), AM_immediate_byte()); break; // PUL (PULU immediate)
|
||||
case 0x35: tick(5); pul(S(), AM_immediate_byte()); break; // PUL (PULS immediate)
|
||||
case 0x37: tick(5); pul(U(), AM_immediate_byte()); break; // PUL (PULU immediate)
|
||||
|
||||
// ROL
|
||||
case 0x09: addCycles(6); BUS().write(rol(AM_direct_byte())); break; // ROL (direct)
|
||||
case 0x49: addCycles(2); A() = rol(A()); break; // ROL (ROLA inherent)
|
||||
case 0x59: addCycles(2); B() = rol(B()); break; // ROL (ROLB inherent)
|
||||
case 0x69: addCycles(6); BUS().write(rol(AM_indexed_byte())); break; // ROL (indexed)
|
||||
case 0x79: addCycles(7); BUS().write(rol(AM_extended_byte())); break; // ROL (extended)
|
||||
case 0x09: tick(6); BUS().write(rol(AM_direct_byte())); break; // ROL (direct)
|
||||
case 0x49: tick(2); A() = rol(A()); break; // ROL (ROLA inherent)
|
||||
case 0x59: tick(2); B() = rol(B()); break; // ROL (ROLB inherent)
|
||||
case 0x69: tick(6); BUS().write(rol(AM_indexed_byte())); break; // ROL (indexed)
|
||||
case 0x79: tick(7); BUS().write(rol(AM_extended_byte())); break; // ROL (extended)
|
||||
|
||||
// ROR
|
||||
case 0x06: addCycles(6); BUS().write(ror(AM_direct_byte())); break; // ROR (direct)
|
||||
case 0x46: addCycles(2); A() = ror(A()); break; // ROR (RORA inherent)
|
||||
case 0x56: addCycles(2); B() = ror(B()); break; // ROR (RORB inherent)
|
||||
case 0x66: addCycles(6); BUS().write(ror(AM_indexed_byte())); break; // ROR (indexed)
|
||||
case 0x76: addCycles(7); BUS().write(ror(AM_extended_byte())); break; // ROR (extended)
|
||||
case 0x06: tick(6); BUS().write(ror(AM_direct_byte())); break; // ROR (direct)
|
||||
case 0x46: tick(2); A() = ror(A()); break; // ROR (RORA inherent)
|
||||
case 0x56: tick(2); B() = ror(B()); break; // ROR (RORB inherent)
|
||||
case 0x66: tick(6); BUS().write(ror(AM_indexed_byte())); break; // ROR (indexed)
|
||||
case 0x76: tick(7); BUS().write(ror(AM_extended_byte())); break; // ROR (extended)
|
||||
|
||||
// RTI
|
||||
case 0x3B: addCycles(6); rti(); break; // RTI (inherent)
|
||||
case 0x3B: tick(6); rti(); break; // RTI (inherent)
|
||||
|
||||
// RTS
|
||||
case 0x39: addCycles(5); rts(); break; // RTS (inherent)
|
||||
case 0x39: tick(5); rts(); break; // RTS (inherent)
|
||||
|
||||
// SBC
|
||||
|
||||
// SBCA
|
||||
case 0x82: addCycles(4); A() = sbc(A(), AM_immediate_byte()); break; // SBC (SBCA immediate)
|
||||
case 0x92: addCycles(4); A() = sbc(A(), AM_direct_byte()); break; // SBC (SBCA direct)
|
||||
case 0xa2: addCycles(4); A() = sbc(A(), AM_indexed_byte()); break; // SBC (SBCA indexed)
|
||||
case 0xb2: addCycles(5); A() = sbc(A(), AM_extended_byte()); break; // SBC (SBCB extended)
|
||||
case 0x82: tick(4); A() = sbc(A(), AM_immediate_byte()); break; // SBC (SBCA immediate)
|
||||
case 0x92: tick(4); A() = sbc(A(), AM_direct_byte()); break; // SBC (SBCA direct)
|
||||
case 0xa2: tick(4); A() = sbc(A(), AM_indexed_byte()); break; // SBC (SBCA indexed)
|
||||
case 0xb2: tick(5); A() = sbc(A(), AM_extended_byte()); break; // SBC (SBCB extended)
|
||||
|
||||
// SBCB
|
||||
case 0xc2: addCycles(4); B() = sbc(B(), AM_immediate_byte()); break; // SBC (SBCB immediate)
|
||||
case 0xd2: addCycles(4); B() = sbc(B(), AM_direct_byte()); break; // SBC (SBCB direct)
|
||||
case 0xe2: addCycles(4); B() = sbc(B(), AM_indexed_byte()); break; // SBC (SBCB indexed)
|
||||
case 0xf2: addCycles(5); B() = sbc(B(), AM_extended_byte()); break; // SBC (SBCB extended)
|
||||
case 0xc2: tick(4); B() = sbc(B(), AM_immediate_byte()); break; // SBC (SBCB immediate)
|
||||
case 0xd2: tick(4); B() = sbc(B(), AM_direct_byte()); break; // SBC (SBCB direct)
|
||||
case 0xe2: tick(4); B() = sbc(B(), AM_indexed_byte()); break; // SBC (SBCB indexed)
|
||||
case 0xf2: tick(5); B() = sbc(B(), AM_extended_byte()); break; // SBC (SBCB extended)
|
||||