Adrian Conlon
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f0376fa81e
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Use macros to define our device pins.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-14 23:17:54 +00:00 |
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Adrian Conlon
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92d23d82d6
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Start big refactor of device/CPU pin usage (to allow pin events throughout).
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-14 02:10:17 +00:00 |
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Adrian Conlon
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87d86bcd84
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Whoops: missed unneeded method declaration.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-09 00:08:03 +00:00 |
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Adrian Conlon
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01175cf9eb
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Add support for emulated SYNC and RDY lines. Untested, but feel close.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-08 23:55:27 +00:00 |
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Adrian Conlon
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047babbe7c
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Rearrange the RESET handler for cycle accuracy. Use more of the general interrupt handler, but with "dummy" stack write access.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-08 23:09:52 +00:00 |
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Adrian Conlon
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25321e78e7
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Now that HALT/RESET/NMI/IRQ and BRK have a unified architecture, I think this wraps up the instruction handler of the 6502.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-08 01:32:43 +00:00 |
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Adrian Conlon
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06e2a5c947
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Start unifying 6502 interrupt handling. NMI/IRQ/BRK are all doing mostly the same work.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-07 01:06:07 +00:00 |
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Adrian Conlon
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c3d2ef51d9
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Cycle accuracy for a couple of the indexed write (store) instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 20:39:37 +00:00 |
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Adrian Conlon
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4d3be9e756
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Use correct boundary crossing conditional for Read/Modify/Write Absolute,X addressing mode.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 12:58:13 +00:00 |
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Adrian Conlon
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baf32cef89
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Get the memory access more correct for more of boundary crossing indexed addressing modes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 12:17:43 +00:00 |
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Adrian Conlon
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3337f57747
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More cycle accuracy changes, concentrating on stack operations.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-05 23:21:43 +00:00 |
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Adrian Conlon
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143e9a9e68
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More cycle accuracy changes:
1) implied instruction, pointless fetch
2) branch pointless fetch when condition is met
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-05 17:23:50 +00:00 |
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Adrian Conlon
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556e06426e
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Further work on the slow migration to a cycle accurate 6502
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-03 01:04:12 +00:00 |
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Adrian Conlon
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5ade05a689
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Add a bunch of undocumented 6502 instructions. Abandoned ATX implementation. Too poorly documented.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-12-30 12:01:23 +00:00 |
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Adrian Conlon
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815c99710a
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Add enough undocumented 6502 instructions to get through "nestest".
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-12-29 22:22:31 +00:00 |
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Adrian Conlon
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c136b306ab
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Use the new busRead/Write processor methods to simplify the 6502 cycle counting.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-12-29 22:18:01 +00:00 |
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Adrian Conlon
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adb60a6e90
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Port the 6502 to the new bus architecture.
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2018-12-29 19:40:02 +00:00 |
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Adrian Conlon
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dc477cd050
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Use explicit enumeration types (improves type safety) where appropriate.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-12-01 15:24:29 +00:00 |
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Adrian Conlon
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003cea0d64
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Make 6502 symbols code a little more like normal C++
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-11-04 13:27:43 +00:00 |
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Adrian Conlon
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8ef5d97366
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Update boost from 1.65 -> 1.68
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-11-04 12:58:01 +00:00 |
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Adrian Conlon
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4dc0becb74
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Refactor the 6502 implementation to be a lot more like the MC6809. Hopefully show bugs in the latter a little more easily.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-10-31 23:29:13 +00:00 |
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Adrian Conlon
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fac2da9ac4
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Start refactoring CPU cores to use C++17/14 features. (This commit covers the 6502 and Z80)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-10-27 18:41:55 +01:00 |
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Adrian Conlon
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1b2ddd8843
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Don't expose the bus via the CPU any more: if a component needs the bus, it should be prepared to hold a reference to it.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-10-20 20:52:41 +01:00 |
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Adrian Conlon
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735f70e717
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Remove a couple of unused headers from the 6502 processor.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-26 19:06:00 +01:00 |
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Adrian Conlon
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1212e8d4f0
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Tidy some processor virtual specifications.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-25 13:35:53 +01:00 |
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Adrian Conlon
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c105ee37bf
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Have a stab at sorting out processor pin handling.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-25 12:09:26 +01:00 |
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Adrian Conlon
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b0aacce406
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Tidy header file usage a little.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-18 23:56:16 +01:00 |
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Adrian Conlon
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cc64e114a9
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Start refactoring the processor classes to allow big/little endian processors to be specified.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-17 21:53:49 +01:00 |
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Adrian Conlon
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70c70af969
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Sort out some exception and member initialisation rules.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-11 21:19:19 +01:00 |
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Adrian Conlon
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cac871cf2b
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Remove duplicated code (from const definitions) the performance benefit isn't worth the amount of duplicated code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-06-24 20:58:20 +01:00 |
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Adrian Conlon
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d27b490d4c
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(Hopefully) fix compilation issue on g++
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-06-16 09:53:44 +01:00 |
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Adrian Conlon
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67487b5b6e
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Simplify the usage of the register16_t union.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-06-16 00:55:32 +01:00 |
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Adrian Conlon
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3e854c7c49
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Const some more bus/processor usage, and ensure the data bus is a member, not a reference to memory.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-06-10 00:40:56 +01:00 |
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Adrian Conlon
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d818095815
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MEMPTR is really only a concept of Intel style processors.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-03-18 22:40:23 +00:00 |
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Adrian Conlon
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45dc274167
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Get rid of wrappers for bus access: i.e. make it clearer where the bus is being read/written.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-03-10 01:53:57 +00:00 |
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Adrian Conlon
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c6eb68ba13
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Further return by value, rather than reference.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-02-26 19:47:35 +00:00 |
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Adrian Conlon
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adf506a41e
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Optimisation: Prefer return by value to return by reference. ~10% speed-up!
Just watch a video by Chandler Carruth from 2015, where he talked about C++ optimisers...
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-02-25 19:48:01 +00:00 |
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Adrian Conlon
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1bf2a9bdfb
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6502, Disassembly: Some dump methods can be static
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-27 10:13:17 +00:00 |
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Adrian Conlon
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9124f10008
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6502: Implement some more undocumented instructions (for the Blargg nes cpu tests)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-21 10:45:25 +00:00 |
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Adrian Conlon
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b5fee5b5d9
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Make explicit the notion of page based loads in M6502.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-18 21:17:45 +00:00 |
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Adrian Conlon
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21bd8a06e6
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Power on conditions are chip specific and *not* directly related to construction/destruction.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-18 17:50:15 +00:00 |
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Adrian Conlon
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19aea5244b
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The vector of instructions was good, but a switch is fastest and probably easiest to read/modify. (Running at 101Mz, 32M instructions per second)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-17 22:17:08 +00:00 |
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Adrian Conlon
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d57cb8c9be
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6502: I might regret this, but move to a vector of instructions, rather than decoding them one at a time
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-16 23:54:43 +00:00 |
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Adrian Conlon
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43573ac699
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6502: Rotate and shift by value, not reference.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-14 21:03:29 +00:00 |
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Adrian Conlon
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ac95670cfc
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Add support for 6502 pin 38 (SO: set overflow)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-12 20:13:35 +00:00 |
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Adrian Conlon
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847e07be86
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Add undocumented 6502 instruction RRA. nestest.nes now runs to completion: Hurrah!
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-07 23:42:26 +00:00 |
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Adrian Conlon
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4d9c0b490a
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Add undocumented 6502 instruction: SRE
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-07 23:16:24 +00:00 |
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Adrian Conlon
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65b856611e
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Undocumented 6502 instruction RLA added.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-07 22:50:14 +00:00 |
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Adrian Conlon
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5b62a6b70b
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Sort out M6502 precompiled headers.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-06 23:19:29 +00:00 |
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Adrian Conlon
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5c3568aebd
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Undocumented instruction: SLO added
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-04 22:46:44 +00:00 |
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