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8b6c4a205e
Commit Graph

48 Commits

Author SHA1 Message Date
Adrian Conlon
8b6c4a205e Lot's of small niggles corrected across the EightBit libraries 2024-03-18 13:03:41 +00:00
Adrian Conlon
b22d7e47e5 Addressing mode simplifications 2024-03-14 14:54:52 +00:00
Adrian Conlon
6599a4ba47 Whoops: missed update to Processor::get/setWordPaged 2024-03-07 09:14:22 +00:00
Adrian Conlon
f3c694303d Low level processor simplifications. 2024-03-01 20:06:39 +00:00
Adrian Conlon
4e536ee7ed Try and sort out problematic "noexcept" specifications (mainly due to events) 2024-01-13 10:24:21 +00:00
Adrian Conlon
4f4bc5355d Simplification of M6502 flag set/reset code 2024-01-07 14:04:41 +00:00
Adrian Conlon
8e0092ec9d Tidy up noexcept specification 2022-01-17 19:10:15 +00:00
Adrian Conlon
1f5dc54c40 Copy constructor and equality operations added. 2021-12-27 22:07:30 +00:00
Adrian Conlon
945fcefb36 Start adding comparison operations to EightBit classes 2021-12-27 14:24:38 +00:00
Adrian Conlon
22506ea56c Extensive change warning: lots of "noexcept" and "constexpr" changes. Not sure if I'll keep all of them, but interesting... 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-07-18 14:28:40 +01:00
Adrian Conlon
d199adb027 Tidy EightBit library header usage (avoids compilation error with latest VS2019, "Memory.h") 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-05-29 10:31:32 +01:00
Adrian Conlon
4d2d1d214a Tidy up some C++ code (concentrating on the Z80 at the moment). 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-01-09 08:41:48 +00:00
Adrian Conlon
b4f8c81a94 Use nodiscard, where appropriate and try not to inline virtual methods. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-01-02 11:49:34 +00:00
Adrian Conlon
44c6a8c3d1 Correct some EightBit project analysis warnings. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2020-04-06 23:11:21 +01:00
Adrian Conlon
c8bdabf34f Reflect that the I/O for Intel style processors isn't part of the CPU, but attached to the Bus and access controlled by the CPU. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2020-02-09 11:51:58 +00:00
Adrian Conlon
20ebbd4048 Start added more .net compatibility methods 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-03 09:23:28 +00:00
Adrian Conlon
f0376fa81e Use macros to define our device pins. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-14 23:17:54 +00:00
Adrian Conlon
92d23d82d6 Start big refactor of device/CPU pin usage (to allow pin events throughout). 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-14 02:10:17 +00:00
Adrian Conlon
f38d326ca7 Improve the flexibility of the BUS mapping/read/write architecture. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-12-29 19:17:36 +00:00
Adrian Conlon
887b89308a Ensure virtual methods are no longer defined inline. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-11-25 10:43:51 +00:00
Adrian Conlon
754fc8e6a3 Refactor the processor class to give us a "Chip" class that gives up pin levels and power. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-23 13:10:58 +01:00
Adrian Conlon
7adefd380a Sort a bunch of missing argument const specifications. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-21 00:16:00 +01:00
Adrian Conlon
dfc4c49454 Correct 5-bit sign extension on the 6809 processor. Allows CLR 5-bit offset indexed disassembly to work correctly. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-27 12:57:44 +01:00
Adrian Conlon
c105ee37bf Have a stab at sorting out processor pin handling. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 12:09:26 +01:00
Adrian Conlon
6d4223c368 Start moving towards reset being just another style of interrupt. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 01:34:30 +01:00
Adrian Conlon
70c70af969 Sort out some exception and member initialisation rules. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-11 21:19:19 +01:00
Adrian Conlon
9de0f597f6 Remove some "tricksy" code from the Z80 emulator chain. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-04-14 09:39:06 +01:00
Adrian Conlon
d818095815 MEMPTR is really only a concept of Intel style processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-18 22:40:23 +00:00
Adrian Conlon
108f66632e Performance: watch out for unnecessary virtualised methods. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-06 17:13:02 +00:00
Adrian Conlon
1edabd79f3 More pinout oriented method of executing instructions (especially interrupts) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-10 21:41:48 +00:00
Adrian Conlon
7e3957d4db Rewrite i8080 interrupts to be more closely related to the hardware. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-02 23:50:59 +00:00
Adrian Conlon
c513f0cab1 GSL was too problematic when used with GCC. Removed. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-20 19:17:49 +00:00
Adrian Conlon
67c27d4a3e GSL + CPP core guidelines changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-18 14:29:30 +00:00
Adrian Conlon
d010e3ca2f Start incorporating CPP core guidelines (as an experiment!) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-10 22:41:50 +00:00
Adrian Conlon
8143f8a506 Try to correct "one definition rule" problems: 
1) No forward declarations
2) No virtual methods defined inline.

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-05 12:47:42 +00:00
Adrian Conlon
c292fb552e A whole bunch of consistency changes. No functional changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-03 22:05:01 +00:00
Adrian.Conlon
64b7335a79 Attempted move to a "BUS" oriented memory architecture (TBC!) 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-09-06 13:22:23 +01:00
Adrian.Conlon
9b43b74c28 Rationalise some of the reset/initialise logic across pProcessor implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-01 16:01:40 +01:00
Adrian.Conlon
406e651c66 Whoops: The processor should only execute instructions while it is powered. Otherwise, it'll get into an infinite loop. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-31 17:19:32 +01:00
Adrian.Conlon
1eb127ed72 Add power support to processor base class. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-31 12:13:00 +01:00
Adrian.Conlon
e70686c5de Some more rationalisation of processor execution/stepping strategies. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-30 23:17:34 +01:00
Adrian.Conlon
3c0a1697fd Fetching bytes/words and stack access are more processor specific than I thought. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-07 09:27:06 +01:00
Adrian.Conlon
c9bf24d1fa Tidy up register and static method access. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-19 13:53:00 +01:00
Adrian.Conlon
627e41bf35 Introduce an IntelProcessor base class to allow known good implementation to be shared. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 09:45:34 +01:00
Adrian.Conlon
b1aa523dcc Small simplifications to base Processor class. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-10 12:42:55 +01:00
Adrian.Conlon
d8977d32d3 More MEMPTR clarifications. 
This time to avoid temporary variables, in a similar manner to Z80 hardware.

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-07 22:54:55 +01:00
Adrian.Conlon
211c75d84d Add Z80 processor and tests. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-05 22:39:15 +01:00
Adrian.Conlon
105032f08a Dump of all my C++ emulators, only Intel8080 integrated so far... 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-04 21:38:34 +01:00