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• f2b9ab0814 Add test for ASLA inherent. Adrian Conlon 2018-10-07 10:32:26 +01:00
• 7719c8e875 Add test for ANDA immediate Adrian Conlon 2018-10-07 10:08:12 +01:00
• 1f4a84b803 Add test for ADDA immediate. Seems to be working. Adrian Conlon 2018-10-07 09:47:10 +01:00
• 5dc185866e Add a test for ADCA immediate. Half carry and overflow flags incorrect! Adrian Conlon 2018-10-07 09:14:30 +01:00
• 7e57efd4cd Modification of unit test comments: no functional modification. Adrian Conlon 2018-10-06 23:54:33 +01:00
• fe05d468d6 Start adding MC6809 unit tests for each instruction. Just ABX, so far Adrian Conlon 2018-10-06 23:52:39 +01:00
• 8048165aab Reorder the output of the M6850 status dump, so it more easily matches the bit order most -> least significant. Adrian Conlon 2018-10-03 20:16:59 +01:00
• 0c174afc02 More MC6809 disassembly corrections: tabs and pshu/s puls/u stack order. Adrian Conlon 2018-10-03 20:15:44 +01:00
• f6cd8a4277 Properly disassemble MC6809 PULS/PULU PSHS/PSHU instructions to show registers. Adrian Conlon 2018-10-02 22:35:31 +01:00
• f58e3ded83 Use corrected MC6850 in MC6809 test board. Working a little better now. Adrian Conlon 2018-09-30 23:10:03 +01:00
• 042e066a0c Correct status handling in the MC6850, and improve documentation. Adrian Conlon 2018-09-30 23:07:07 +01:00
• 8ea7bf5d68 Refactoring on the MC6850 and associated test board code. Adrian Conlon 2018-09-29 14:31:50 +01:00
• 8d3551e681 Refactor bit set/get routines from processor class to lower level chip class. Adrian Conlon 2018-09-29 14:08:44 +01:00
• de5a9963e0 More MC6850 updates Adrian Conlon 2018-09-29 10:06:02 +01:00
• f6bd871757 Whoops: correct 6809 stack pointer increment/decrement order Adrian Conlon 2018-09-29 10:02:53 +01:00
• 861fc28bba Wire up the MC6850 events to the board Adrian Conlon 2018-09-25 23:57:20 +01:00
• df7c7904f4 Whoops: correct a small layout (tabs) issue. Adrian Conlon 2018-09-25 23:56:28 +01:00
• 4f567c75f9 Probably doesn't work, but this is another style of MC6850 event handling Adrian Conlon 2018-09-25 23:55:14 +01:00
• 9ab075d0f6 Incorporate the concepts of transmission and receipt into the events for the MC6850 (TBC) Adrian Conlon 2018-09-24 08:29:11 +01:00
• d77c2a1e9d Add more of the MC6850 internals. Adrian Conlon 2018-09-23 20:31:55 +01:00
• b3faa0bb2e Wire the MC6850 chip into the MC6809 test code. Adrian Conlon 2018-09-23 13:14:10 +01:00
• 754fc8e6a3 Refactor the processor class to give us a "Chip" class that gives up pin levels and power. Adrian Conlon 2018-09-23 13:10:58 +01:00
• 91349eafa4 Updated MC6850 documentation. Bit more searchable... Adrian Conlon 2018-09-23 10:19:39 +01:00
• be2f5abdb5 Correct a couple of small layout issues in the MC6850 code Adrian Conlon 2018-09-23 00:08:16 +01:00
• e2f69b1dc8 Start adding support for the Motorola serial device, the MC6850 ACIA (most incomplete!) Adrian Conlon 2018-09-22 23:11:13 +01:00
• 30ac7dc268 Whoops: missed movement of stdafx.h for MC6809 Adrian Conlon 2018-09-22 23:09:10 +01:00
• d45401d9b1 Tidy a couple of MC6809 niggles: Adrian Conlon 2018-09-22 10:54:05 +01:00
• 7c03521025 Refactor plsu/s pshu/s to share code more easily Adrian Conlon 2018-09-21 00:28:08 +01:00
• 6bb8118c7f Add miscellaneous documentation and test gubbins Adrian Conlon 2018-09-21 00:17:25 +01:00
• 7adefd380a Sort a bunch of missing argument const specifications. Adrian Conlon 2018-09-21 00:16:00 +01:00
• 9e91d2adad Plug the 8K hole in the address space of the Grant Searle SBC with 0xff (held high) Adrian Conlon 2018-09-16 19:49:52 +01:00
• 54bb9743be Correct 10/11 opcode prefix disassembly on the 6809 processor. Adrian Conlon 2018-09-16 17:56:55 +01:00
• 2d93087e5f Correct the hex loader, using the new mapping mechanism. Adrian Conlon 2018-09-16 17:54:53 +01:00
• fe3794e011 Simplify register16_t usage a little. Adrian Conlon 2018-09-16 12:00:29 +01:00
• 6256d0bf8d Correct compilation warnings. Adrian Conlon 2018-09-15 18:33:33 +01:00
• 7d840f1a42 Modifying the manner in which memory is mapped, allows a fairly clean mechanism for loading Intel "hex" files. Adrian Conlon 2018-09-15 14:35:59 +01:00
• a9adde6ea5 Correct 6809 CLR flag handling. Adrian Conlon 2018-08-30 01:37:46 +01:00
• 8e0c1ebcde Modify the 6809 disassembler a little to give output more like xroar (for comparison purposes) Adrian Conlon 2018-08-30 01:37:09 +01:00
• c85176431b Refactor 6809 jsr/rts code a little. No functional changes. Adrian Conlon 2018-08-29 14:03:24 +01:00
• 97272d650d Simplify processor bus access a little by further allowing register16_t address access. Adrian Conlon 2018-08-29 13:52:25 +01:00
• 46b140dda1 Correct issues with the 6809 indirect indexed addressing mode. Adrian Conlon 2018-08-29 13:25:19 +01:00
• b0addc5100 Correct a couple of minor issues in the 6809 disassembler Adrian Conlon 2018-08-28 18:28:00 +01:00
• 52ad4e6996 Tidied the 6809 disassembler a little. Adrian Conlon 2018-08-28 16:46:15 +01:00
• 3dfea03b2e In theory, this finishes the 6809 disassembler. Adrian Conlon 2018-08-28 13:56:06 +01:00
• 67b5fe1658 Add two more pieces of 6809 documentation Adrian Conlon 2018-08-28 08:30:56 +01:00
• c22b3fca3b Correct 6809 disassembly prefix issue. Adrian Conlon 2018-08-28 08:18:00 +01:00
• 837ac495ab Couple more 6809 disassembly instructions added, up to the point of an instruction oddity... Adrian Conlon 2018-08-27 23:50:18 +01:00
• ce9738eb4b Fill out more 6809 disassembly + fix a bug in the TFR/EXG instructions: muddled up 8/16 bit transfers. Adrian Conlon 2018-08-27 22:48:08 +01:00
• fbc743a608 6809 Disassembly: Addressing mode: immediate byte added. More instructions decoded. Adrian Conlon 2018-08-27 13:11:43 +01:00
• dfc4c49454 Correct 5-bit sign extension on the 6809 processor. Allows CLR 5-bit offset indexed disassembly to work correctly. Adrian Conlon 2018-08-27 12:57:44 +01:00
• 2f632cdaf5 Another 6809 instruction and addressing mode disassembly added. Adrian Conlon 2018-08-27 11:29:15 +01:00
• a8cc289149 Whoops: The "Bus" class *really* isn't allowed to know the "endianness" of the attached processor! Adrian Conlon 2018-08-27 11:27:33 +01:00
• a5e51f7140 Simplify the 6809 disassembler usage a little. Adrian Conlon 2018-08-27 10:43:12 +01:00
• 974d5fbd14 Only show disassembled output, when there is actually something to show (fixes 6809 startup/interrupt sequence) Adrian Conlon 2018-08-27 10:25:15 +01:00
• 983e2a5eb2 Start fleshing out the 6809 disassembler. Adrian Conlon 2018-08-27 01:19:22 +01:00
• 87b7295fe8 Remove unused "Resource" folder from the 6809 test project Adrian Conlon 2018-08-27 01:18:49 +01:00
• 2d6b9d9ecf Add some more 6809 documentation. Adrian Conlon 2018-08-26 19:10:04 +01:00
• e88cbc269b Add a skeletal half way house between a 6809 tester and a CoCo 2 emulator. Adrian Conlon 2018-08-26 19:09:34 +01:00
• a22c5a5c78 Add skeletal disassembler to the 6809 processor. Adrian Conlon 2018-08-26 19:08:07 +01:00
• 735f70e717 Remove a couple of unused headers from the 6502 processor. Adrian Conlon 2018-08-26 19:06:00 +01:00
• 50826d36b6 Add a little pin documentation to the 6809 processor. Adrian Conlon 2018-08-26 19:02:41 +01:00
• dc6803a5b6 Whoops: powerOn should always be public (6809) Adrian Conlon 2018-08-26 17:27:50 +01:00
• ef5e325b6d Tidy 6809 header file usage a little. Adrian Conlon 2018-08-26 13:07:26 +01:00
• c03d8488b5 Allow memory peek as a const operation. Adrian Conlon 2018-08-26 13:06:05 +01:00
• 8823bb6610 Refactor the *EndianProcessor classes, such that their implementation is no longer in header files. Adrian Conlon 2018-08-25 22:51:56 +01:00
• 3a4235f651 Whoops: The NMI line needs to be powered on by individual processors now it's no longer part of the Processor base class. Adrian Conlon 2018-08-25 22:50:18 +01:00
• ab78ba5db0 Start adding definition of BA/BS flags. Adrian Conlon 2018-08-25 14:55:57 +01:00
• 1212e8d4f0 Tidy some processor virtual specifications. Adrian Conlon 2018-08-25 13:35:53 +01:00
• 535346dede Whoops: missed UNLIKELY specifier on the 6502 processor Adrian Conlon 2018-08-25 13:17:14 +01:00
• ae66b39dac Add a couple of LIKELY/UNLIKELY specifications to the 6809 processor. Adrian Conlon 2018-08-25 12:51:43 +01:00
• c105ee37bf Have a stab at sorting out processor pin handling. Adrian Conlon 2018-08-25 12:09:26 +01:00
• 17c46264e9 Match the GameBoy code to the updated handling of reset (etc.) interrupts. Adrian Conlon 2018-08-25 01:57:22 +01:00
• 6d4223c368 Start moving towards reset being just another style of interrupt. Adrian Conlon 2018-08-25 01:34:30 +01:00
• bca7977a23 Whoops: correctly generalise DAA code on the 6809 Adrian Conlon 2018-08-24 13:05:29 +01:00
• f8097af5a4 Whoops: correct overly enthusiastic shift on the 6809 Adrian Conlon 2018-08-24 12:57:04 +01:00
• 0649796575 Small code tidy in the 6809 Adrian Conlon 2018-08-24 12:36:25 +01:00
• adb6433737 Easier to read flag handling in the 6809 Adrian Conlon 2018-08-24 12:30:16 +01:00
• 21e8360dc1 First stab at interrupt handling on the 6809 processor. Adrian Conlon 2018-08-24 12:14:14 +01:00
• 1eb59279a8 Remove unneeded powerOn override from the 6809 processor. Adrian Conlon 2018-08-24 10:54:16 +01:00
• 57928602d5 Tidy instruction prefixing in the 6809, such that executed/ing instruction events fire correctly. Adrian Conlon 2018-08-24 10:49:13 +01:00
• a43b1109bc Add TST instruction to the 6809 processor Adrian Conlon 2018-08-24 00:33:18 +01:00
• c7ca555995 Add various SUB/SBC instructions to the 6809 processor Adrian Conlon 2018-08-24 00:14:44 +01:00
• 595a9a0af7 Tidy the formatting within the 6809 processor code. Adrian Conlon 2018-08-23 23:22:14 +01:00
• 722e7b89c2 Add implementation of ST instruction for the 6809 Adrian Conlon 2018-08-23 23:09:19 +01:00
• 1e32514e1d Implement SEX/SWI/SWI2/SWI3/SYNC/TFR instructions for the 6809 Adrian Conlon 2018-08-23 14:09:46 +01:00
• e555fe335f Whoops: correct return values of 6809 branch helpers. Adrian Conlon 2018-08-23 09:32:37 +01:00
• 6af8641b45 Tidy instruction comments a little on the 6809 Adrian Conlon 2018-08-23 09:22:17 +01:00
• 224c254223 Add stubs for any remaining instruction sin the 6809 processor. Adrian Conlon 2018-08-23 00:43:56 +01:00
• 4703b89a42 First stab at 6809 branching Adrian Conlon 2018-08-22 23:06:36 +01:00
• 90fb124bd7 Whoops: RTI is 3B in the 6809 processor Adrian Conlon 2018-08-22 10:24:12 +01:00
• 10684a02f4 Add RTI/RTS instructions to the 6809 processor Adrian Conlon 2018-08-22 10:21:22 +01:00
• 07248972bf Add implementations of ROL/ROR for the 6809 processor Adrian Conlon 2018-08-22 09:11:02 +01:00
• 6f6e88f003 Tidy up instruction timing for the PUL/PSH instructions on the 6809 Adrian Conlon 2018-08-22 08:45:38 +01:00
• 117f03cbd1 Whoops: Correct PULS/PSHU/PULU instructions on the 6809 Adrian Conlon 2018-08-22 08:19:44 +01:00
• 1556e82313 Whoops: CWAI has to flag that the entire range of registers has been saved. (6809) Adrian Conlon 2018-08-22 01:03:54 +01:00
• 86c9ade43f Add PSH/PUL instructions to the 6809 processor Adrian Conlon 2018-08-22 00:34:16 +01:00
• 905e7d3d44 Whoops: Correct cycle counts for the OR instruction on the 6809 Adrian Conlon 2018-08-21 23:09:04 +01:00
• 551c26bb3c Add OR instruction to the 6809 processor Adrian Conlon 2018-08-21 23:07:22 +01:00
• 06f4300c38 Added MUL instruction to the 6809 processor. Adrian Conlon 2018-08-21 22:45:33 +01:00
• c571956377 Add LSR implementation to the 6809 processor Adrian Conlon 2018-08-21 21:59:25 +01:00