mirror of
https://github.com/MoleskiCoder/EightBit.git
synced 2026-03-11 04:41:57 +00:00
602 lines
12 KiB
C++
602 lines
12 KiB
C++
#include "stdafx.h"
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#include "Intel8080.h"
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EightBit::Intel8080::Intel8080(Memory& memory, InputOutput& ports)
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: IntelProcessor(memory),
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m_interrupt(false),
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m_ports(ports) {
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bc.word = de.word = hl.word = Mask16;
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}
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void EightBit::Intel8080::di() {
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m_interrupt = false;
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}
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void EightBit::Intel8080::ei() {
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m_interrupt = true;
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}
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int EightBit::Intel8080::interrupt(uint8_t value) {
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if (isInterruptable()) {
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di();
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return execute(value);
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}
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return 0;
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}
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bool EightBit::Intel8080::isInterruptable() const {
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return m_interrupt;
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}
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void EightBit::Intel8080::increment(uint8_t& f, uint8_t& operand) {
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adjustSZP<Intel8080>(f, ++operand);
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clearFlag(f, AC, lowNibble(operand));
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}
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void EightBit::Intel8080::decrement(uint8_t& f, uint8_t& operand) {
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adjustSZP<Intel8080>(f, --operand);
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setFlag(f, AC, lowNibble(operand) != Mask4);
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}
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bool EightBit::Intel8080::jumpConditionalFlag(uint8_t& f, int flag) {
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switch (flag) {
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case 0: // NZ
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return jumpConditional(!(f & ZF));
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case 1: // Z
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return jumpConditional(f & ZF);
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case 2: // NC
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return jumpConditional(!(f & CF));
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case 3: // C
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return jumpConditional(f & CF);
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case 4: // PO
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return jumpConditional(!(f & PF));
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case 5: // PE
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return jumpConditional(f & PF);
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case 6: // P
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return jumpConditional(!(f & SF));
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case 7: // M
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return jumpConditional(f & SF);
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default:
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UNREACHABLE;
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}
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throw std::logic_error("Unhandled JP conditional");
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}
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bool EightBit::Intel8080::returnConditionalFlag(uint8_t& f, int flag) {
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switch (flag) {
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case 0: // NZ
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return returnConditional(!(f & ZF));
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case 1: // Z
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return returnConditional(f & ZF);
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case 2: // NC
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return returnConditional(!(f & CF));
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case 3: // C
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return returnConditional(f & CF);
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case 4: // PO
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return returnConditional(!(f & PF));
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case 5: // PE
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return returnConditional(f & PF);
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case 6: // P
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return returnConditional(!(f & SF));
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case 7: // M
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return returnConditional(f & SF);
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default:
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UNREACHABLE;
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}
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throw std::logic_error("Unhandled RET conditional");
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}
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bool EightBit::Intel8080::callConditionalFlag(uint8_t& f, int flag) {
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switch (flag) {
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case 0: // NZ
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return callConditional(!(f & ZF));
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case 1: // Z
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return callConditional(f & ZF);
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case 2: // NC
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return callConditional(!(f & CF));
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case 3: // C
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return callConditional(f & CF);
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case 4: // PO
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return callConditional(!(f & PF));
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case 5: // PE
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return callConditional(f & PF);
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case 6: // P
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return callConditional(!(f & SF));
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case 7: // M
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return callConditional(f & SF);
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default:
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UNREACHABLE;
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}
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throw std::logic_error("Unhandled CALL conditional");
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}
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void EightBit::Intel8080::add(uint8_t& f, register16_t& operand, register16_t value) {
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const auto result = operand.word + value.word;
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setFlag(f, CF, result & Bit16);
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operand.word = result;
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}
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void EightBit::Intel8080::add(uint8_t& f, uint8_t& operand, uint8_t value, int carry) {
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register16_t result;
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result.word = operand + value + carry;
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adjustAuxiliaryCarryAdd(f, operand, value, result.word);
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operand = result.low;
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setFlag(f, CF, result.word & Bit8);
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adjustSZP<Intel8080>(f, operand);
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}
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void EightBit::Intel8080::adc(uint8_t& f, uint8_t& operand, uint8_t value) {
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add(f, operand, value, f & CF);
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}
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void EightBit::Intel8080::subtract(uint8_t& f, uint8_t& operand, uint8_t value, int carry) {
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register16_t result;
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result.word = operand - value - carry;
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adjustAuxiliaryCarrySub(f, operand, value, result.word);
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operand = result.low;
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setFlag(f, CF, result.word & Bit8);
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adjustSZP<Intel8080>(f, operand);
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}
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void EightBit::Intel8080::sbb(uint8_t& f, uint8_t& operand, uint8_t value) {
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subtract(f, operand, value, f & CF);
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}
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void EightBit::Intel8080::andr(uint8_t& f, uint8_t& operand, uint8_t value) {
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setFlag(f, AC, (operand | value) & Bit3);
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clearFlag(f, CF);
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adjustSZP<Intel8080>(f, operand &= value);
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}
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void EightBit::Intel8080::xorr(uint8_t& f, uint8_t& operand, uint8_t value) {
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clearFlag(f, AC | CF);
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adjustSZP<Intel8080>(f, operand ^= value);
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}
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void EightBit::Intel8080::orr(uint8_t& f, uint8_t& operand, uint8_t value) {
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clearFlag(f, AC | CF);
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adjustSZP<Intel8080>(f, operand |= value);
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}
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void EightBit::Intel8080::compare(uint8_t& f, uint8_t check, uint8_t value) {
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subtract(f, check, value);
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}
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void EightBit::Intel8080::rlc(uint8_t& f, uint8_t& operand) {
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auto carry = operand & Bit7;
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operand = (operand << 1) | (carry >> 7);
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setFlag(f, CF, carry);
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}
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void EightBit::Intel8080::rrc(uint8_t& f, uint8_t& operand) {
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auto carry = operand & Bit0;
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operand = (operand >> 1) | (carry << 7);
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setFlag(f, CF, carry);
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}
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void EightBit::Intel8080::rl(uint8_t& f, uint8_t& operand) {
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const auto carry = f & CF;
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setFlag(f, CF, operand & Bit7);
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operand = (operand << 1) | carry;
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}
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void EightBit::Intel8080::rr(uint8_t& f, uint8_t& operand) {
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const auto carry = f & CF;
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setFlag(f, CF, operand & Bit0);
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operand = (operand >> 1) | (carry << 7);
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}
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void EightBit::Intel8080::daa(uint8_t& a, uint8_t& f) {
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const auto& before = a;
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auto carry = f & CF;
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uint8_t addition = 0;
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if ((f & AC) || lowNibble(before) > 9) {
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addition = 0x6;
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}
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if ((f & CF) || highNibble(before) > 9 || (highNibble(before) >= 9 && lowNibble(before) > 9)) {
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addition |= 0x60;
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carry = true;
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}
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add(f, a, addition);
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setFlag(f, CF, carry);
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}
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void EightBit::Intel8080::cma(uint8_t& a, uint8_t& f) {
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a = ~a;
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}
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void EightBit::Intel8080::stc(uint8_t& a, uint8_t& f) {
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setFlag(f, CF);
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}
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void EightBit::Intel8080::cmc(uint8_t& a, uint8_t& f) {
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clearFlag(f, CF, f & CF);
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}
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void EightBit::Intel8080::xhtl() {
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MEMPTR().low = getByte(SP());
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setByte(L());
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L() = MEMPTR().low;
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m_memory.ADDRESS().word++;
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MEMPTR().high = getByte();
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setByte(H());
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H() = MEMPTR().high;
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}
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void EightBit::Intel8080::out() {
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m_ports.write(fetchByte(), A());
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}
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void EightBit::Intel8080::in() {
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A() = m_ports.read(fetchByte());
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}
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int EightBit::Intel8080::step() {
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ExecutingInstruction.fire(*this);
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cycles = 0;
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return fetchExecute();
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}
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int EightBit::Intel8080::execute(uint8_t opcode) {
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const auto& decoded = getDecodedOpcode(opcode);
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auto x = decoded.x;
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auto y = decoded.y;
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auto z = decoded.z;
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auto p = decoded.p;
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auto q = decoded.q;
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execute(x, y, z, p, q);
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if (cycles == 0)
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throw std::logic_error("Unhandled opcode");
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return cycles;
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}
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void EightBit::Intel8080::execute(int x, int y, int z, int p, int q) {
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auto& a = A();
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auto& f = F();
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switch (x) {
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case 0:
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switch (z) {
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case 0: // Relative jumps and assorted ops
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switch (y) {
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case 0: // NOP
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cycles += 4;
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break;
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}
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break;
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case 1: // 16-bit load immediate/add
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switch (q) {
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case 0: // LD rp,nn
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Processor::fetchWord(RP(p));
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cycles += 10;
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break;
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case 1: // ADD HL,rp
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add(f, HL(), RP(p));
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cycles += 11;
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break;
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}
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break;
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case 2: // Indirect loading
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switch (q) {
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case 0:
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switch (p) {
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case 0: // LD (BC),A
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MEMPTR() = BC();
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memptrReference();
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setByte(MEMPTR().high = a);
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cycles += 7;
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break;
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case 1: // LD (DE),A
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MEMPTR() = DE();
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memptrReference();
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setByte(MEMPTR().high = a);
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cycles += 7;
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break;
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case 2: // LD (nn),HL
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fetchWord();
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setWordViaMemptr(HL());
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cycles += 16;
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break;
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case 3: // LD (nn),A
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fetchWord();
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memptrReference();
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setByte(MEMPTR().high = a);
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cycles += 13;
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break;
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default:
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UNREACHABLE;
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}
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break;
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case 1:
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switch (p) {
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case 0: // LD A,(BC)
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MEMPTR() = BC();
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memptrReference();
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a = getByte();
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cycles += 7;
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break;
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case 1: // LD A,(DE)
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MEMPTR() = DE();
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memptrReference();
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a = getByte();
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cycles += 7;
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break;
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case 2: // LD HL,(nn)
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fetchWord();
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getWordViaMemptr(HL());
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cycles += 16;
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break;
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case 3: // LD A,(nn)
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fetchWord();
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memptrReference();
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a = getByte();
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cycles += 13;
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break;
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default:
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UNREACHABLE;
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}
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break;
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default:
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UNREACHABLE;
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}
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break;
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case 3: // 16-bit INC/DEC
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switch (q) {
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case 0: // INC rp
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++RP(p).word;
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break;
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case 1: // DEC rp
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--RP(p).word;
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break;
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default:
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UNREACHABLE;
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}
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cycles += 6;
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break;
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case 4: { // 8-bit INC
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auto operand = R(y);
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increment(f, operand);
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R(y, operand);
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cycles += 4;
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break;
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} case 5: { // 8-bit DEC
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auto operand = R(y);
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decrement(f, operand);
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R(y, operand);
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cycles += 4;
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if (y == 6)
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cycles += 7;
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break;
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} case 6: // 8-bit load immediate
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R(y, fetchByte());
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cycles += 7;
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if (y == 6)
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cycles += 3;
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y) {
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case 0:
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rlc(f, a);
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break;
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case 1:
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rrc(f, a);
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break;
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case 2:
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rl(f, a);
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break;
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case 3:
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rr(f, a);
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break;
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case 4:
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daa(a, f);
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break;
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case 5:
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cma(a, f);
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break;
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case 6:
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stc(a, f);
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break;
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case 7:
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cmc(a, f);
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break;
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default:
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UNREACHABLE;
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}
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cycles += 4;
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break;
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default:
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UNREACHABLE;
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}
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break;
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case 1: // 8-bit loading
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if (z == 6 && y == 6) { // Exception (replaces LD (HL), (HL))
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halt();
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} else {
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R(y, R(z));
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if ((y == 6) || (z == 6)) // M operations
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cycles += 3;
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}
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cycles += 4;
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break;
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case 2: // Operate on accumulator and register/memory location
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switch (y) {
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case 0: // ADD A,r
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add(f, a, R(z));
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break;
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case 1: // ADC A,r
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adc(f, a, R(z));
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break;
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case 2: // SUB r
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subtract(f, a, R(z));
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break;
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case 3: // SBC A,r
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sbb(f, a, R(z));
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break;
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case 4: // AND r
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andr(f, a, R(z));
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break;
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case 5: // XOR r
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xorr(f, a, R(z));
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break;
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case 6: // OR r
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orr(f, a, R(z));
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break;
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case 7: // CP r
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compare(f, a, R(z));
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break;
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default:
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UNREACHABLE;
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}
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cycles += 4;
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if (z == 6)
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cycles += 3;
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break;
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case 3:
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switch (z) {
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case 0: // Conditional return
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if (returnConditionalFlag(f, y))
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cycles += 6;
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cycles += 5;
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break;
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case 1: // POP & various ops
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switch (q) {
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case 0: // POP rp2[p]
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popWord(RP2(p));
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cycles += 10;
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break;
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case 1:
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switch (p) {
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case 0: // RET
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ret();
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cycles += 10;
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break;
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case 2: // JP HL
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PC() = HL();
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cycles += 4;
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break;
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case 3: // LD SP,HL
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SP() = HL();
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cycles += 4;
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break;
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}
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break;
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default:
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UNREACHABLE;
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}
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break;
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case 2: // Conditional jump
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jumpConditionalFlag(f, y);
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cycles += 10;
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break;
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case 3: // Assorted operations
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switch (y) {
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case 0: // JP nn
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fetchWord();
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jump();
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cycles += 10;
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break;
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case 2: // OUT (n),A
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out();
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cycles += 11;
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break;
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case 3: // IN A,(n)
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in();
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cycles += 11;
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break;
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case 4: // EX (SP),HL
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xhtl();
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cycles += 19;
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break;
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case 5: // EX DE,HL
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std::swap(DE(), HL());
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cycles += 4;
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break;
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case 6: // DI
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di();
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cycles += 4;
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break;
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case 7: // EI
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ei();
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cycles += 4;
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break;
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}
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break;
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case 4: // Conditional call: CALL cc[y], nn
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if (callConditionalFlag(f, y))
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cycles += 7;
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cycles += 10;
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break;
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case 5: // PUSH & various ops
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switch (q) {
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case 0: // PUSH rp2[p]
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pushWord(RP2(p));
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cycles += 11;
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break;
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case 1:
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switch (p) {
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case 0: // CALL nn
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fetchWord();
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call();
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cycles += 17;
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break;
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}
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break;
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default:
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UNREACHABLE;
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}
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break;
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case 6: // Operate on accumulator and immediate operand: alu[y] n
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switch (y) {
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case 0: // ADD A,n
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add(f, a, fetchByte());
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break;
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case 1: // ADC A,n
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adc(f, a, fetchByte());
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break;
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case 2: // SUB n
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subtract(f, a, fetchByte());
|
|
break;
|
|
case 3: // SBC A,n
|
|
sbb(f, a, fetchByte());
|
|
break;
|
|
case 4: // AND n
|
|
andr(f, a, fetchByte());
|
|
break;
|
|
case 5: // XOR n
|
|
xorr(f, a, fetchByte());
|
|
break;
|
|
case 6: // OR n
|
|
orr(f, a, fetchByte());
|
|
break;
|
|
case 7: // CP n
|
|
compare(f, a, fetchByte());
|
|
break;
|
|
default:
|
|
UNREACHABLE;
|
|
}
|
|
cycles += 7;
|
|
break;
|
|
case 7: // Restart: RST y * 8
|
|
restart(y << 3);
|
|
cycles += 11;
|
|
break;
|
|
default:
|
|
UNREACHABLE;
|
|
}
|
|
break;
|
|
}
|
|
}
|