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Add an extra Z80 interrupt test
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@@ -115,7 +115,10 @@ namespace Z80.UnitTests
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[TestMethod]
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public void Int_IM0_Executes_Instruction_From_Data_Bus()
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{
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// RST 7 (0xFF) placed on data bus by interrupt device → jumps to 0x0038
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// RST 7 (0xFF) placed on data bus by interrupt device → jumps to 0x0038.
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// In practice IM 0 is always used with RST n (single-byte). The Zilog
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// spec technically allows multi-byte instructions inherited from the 8080,
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// but no real Z80 peripheral (PIO, SIO, CTC) ever used that capability.
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this.cpu.PC.Joined = 0x0200;
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this.cpu.IM = 0;
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this.board.Data = 0xFF; // RST 7
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@@ -143,5 +146,30 @@ namespace Z80.UnitTests
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this.cpu.Step(); // executes RETI
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Assert.AreEqual(0x0200, this.cpu.PC.Joined, "RETI must restore PC from stack");
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}
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[TestMethod]
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public void Reti_Restores_IFF1_From_IFF2()
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{
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// On real Z80 silicon RETI and RETN are electrically identical — both
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// copy IFF2 → IFF1. The Zilog manual omits this for RETI (describing
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// only its peripheral daisy-chain signalling role), but hardware
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// measurement confirms the behaviour. RetI() is implemented as RetN().
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this.board.Poke(0x0038, 0xED);
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this.board.Poke(0x0039, 0x4D); // RETI
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this.cpu.IFF2 = true; // pre-load IFF2 with the state to restore
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this.cpu.IM = 1;
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this.cpu.LowerINT();
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this.cpu.Step(); // INT clears IFF1 and IFF2, jumps to 0x0038
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Assert.IsFalse(this.cpu.IFF1, "INT must clear IFF1 before RETI");
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Assert.IsFalse(this.cpu.IFF2, "INT must clear IFF2 before RETI");
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// Manually set IFF2 to simulate what a real ISR would have saved
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this.cpu.IFF2 = true;
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this.cpu.Step(); // executes RETI — must copy IFF2 → IFF1
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Assert.IsTrue(this.cpu.IFF1, "RETI must copy IFF2 into IFF1");
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}
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}
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}
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