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Power-on and reset consistency fixes

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This commit is contained in:
Adrian Conlon
2025-05-06 11:52:33 +01:00
parent e1696721f6
commit d58095a9d0
2 changed files with 13 additions and 8 deletions
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EightBit/IntelProcessor.cs
+2 -7
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@@ -102,12 +102,6 @@ namespace EightBit
return this.HALT.Lowered() ? (byte)0 : read;
}
protected void ResetWorkingRegisters()
{
this.AF.Word = this.BC.Word = this.DE.Word = this.HL.Word = (ushort)Mask.Sixteen;
}
protected static int BuildHalfCarryIndex(byte before, byte value, int calculation) => ((before & 0x88) >> 1) | ((value & 0x88) >> 2) | ((calculation & 0x88) >> 3);
protected static int CalculateHalfCarryAdd(byte before, byte value, int calculation)
@@ -124,7 +118,8 @@ namespace EightBit
private void IntelProcessor_RaisedPOWER(object? sender, EventArgs e)
{
this.PC.Word = this.SP.Word = this.AF.Word = this.BC.Word = this.DE.Word = this.HL.Word = (ushort)Mask.Sixteen;
this.PC.Word = this.SP.Word = (ushort)Mask.Sixteen;
this.AF.Word = this.BC.Word = this.DE.Word = this.HL.Word = (ushort)Mask.Sixteen;
this.RaiseHALT();
}
Z80/Z80.cs
+11 -1
View File
@@ -192,7 +192,6 @@ namespace Z80
this.Exx();
this.IX.Word = this.IY.Word = (ushort)Mask.Sixteen;
base.ResetWorkingRegisters();
this.ResetPrefixes();
}
@@ -520,10 +519,21 @@ namespace Z80
return returned;
}
// From Zilog Z80 manual
// https://www.zilog.com/docs/z80/um0080.pdf
//
// RESET. Reset (input, active Low).
// _____
// RESET initializes the CPU as follows: it resets the
// interrupt enable flip-flop, clears the Program Counter and registers I and R, and sets the
// interrupt status to Mode 0. During reset time, the address and data bus enter a high-impedance
// state, and all control output signals enter an inactive state.RESET must be active for
// a minimum of three full clock cycles before a reset operation is complete.
protected override void HandleRESET()
{
base.HandleRESET();
this.IV = this.REFRESH = 0;
this.IM = 0;
this.SP.Word = this.AF.Word = (ushort)Mask.Sixteen;
this.Tick(3);
}