6502/EightBitNet
1
0
Fork 0
mirror of https://github.com/MoleskiCoder/EightBitNet.git synced 2026-04-19 15:16:41 +00:00
Code Issues Projects Releases Wiki Activity
396 Commits 1 Branch 0 Tags
a0d45eace122de62b652dac67ca2052f59bcce4e
Commit Graph

70 Commits

Author SHA1 Message Date
Adrian Conlon 26457b4a77 Correct timing for 16-bit arithmetic tests. 26 failures remaining 2025-05-03 15:03:04 +01:00
Adrian Conlon 68328d92fb Fix displaced timing on arithmetic operations for z80. 34 failures now 2025-05-03 14:40:38 +01:00
Adrian Conlon 506e2b9eda Fix some displaced memory load timing issues. 50 issues remaining. 2025-05-03 14:10:18 +01:00
Adrian Conlon f9754dd62f Fix some z80 eight-bit load timing issues. 58 issues remaining 2025-05-03 13:54:18 +01:00
Adrian Conlon 9f2079efae More z80 timing issues fixed. 70 issues remain 2025-05-03 13:21:36 +01:00
Adrian Conlon 080f203a55 Unify Intel style JR CC code and fix SM83 timing issues. 2025-05-03 12:09:34 +01:00
Adrian Conlon 94b8da456b Fix loads of z80 timing issues. 84 timing issues remain. 2025-05-03 11:45:55 +01:00
Adrian Conlon 946121defb Fix HALT instruction 2025-05-03 02:08:52 +01:00
Adrian Conlon 561483d65d More timing fixes. 255 timing errors 2025-05-03 01:31:44 +01:00
Adrian Conlon f4f4357a3e More z80 timing fixes, 261 errors 2025-05-03 00:51:20 +01:00
Adrian Conlon e1aa220409 Further Z80 timing fixes: 290 failures 2025-05-03 00:09:19 +01:00
Adrian Conlon 175069d6bf More Z80 timing fixes 2025-05-02 20:18:04 +01:00
Adrian Conlon 3617608e8c Fix a number of write timing issues 2025-05-02 17:46:33 +01:00
Adrian Conlon fda52af260 Only DJNZ has the extra tick (presumably to decrement the B register) 2025-05-02 14:07:15 +01:00
Adrian Conlon 935466ad6f Correct timing issues both conditional and unconditional relative jumpson Z80 2025-05-02 14:03:15 +01:00
Adrian Conlon 9670c3fd21 Start correcting timing issues in my Z80 implementation 2025-05-02 12:11:54 +01:00
Adrian Conlon dd1d141f15 Simplify conditional flag handling in intel processors 2025-04-29 12:27:39 +01:00
Adrian Conlon 1b1b92ac2c More event handling simplification 2025-03-29 13:18:54 +00:00
Adrian Conlon 3d6b549c76 Turns out using lambdas to control pins is lovely and correct, but terribly slow. Back to a more traditional method. 2025-03-24 20:18:04 +00:00
Adrian Conlon d4dc99b454 Use lambda functions to simplify CPU pin control 2025-03-23 11:08:36 +00:00
Adrian Conlon a9db2f58bd miscellaneous fixes, especiall flags 2025-03-18 18:38:47 +00:00
Adrian Conlon e8d770c6bb Simplify i/o port handling in Z80 implementation 2025-01-27 21:23:47 +00:00
Adrian Conlon f6829f2ec0 Z80 .net 9 analysis changes 2024-10-12 12:09:22 +01:00
Adrian Conlon 3cbc7f32d2 More analysis fixes 2024-10-09 22:46:25 +01:00
Adrian Conlon 647be6f224 More style changes 2024-10-09 21:16:55 +01:00
Adrian Conlon d67cafe297 Prefer a more straightforward register exchange 2024-09-27 12:43:14 +01:00
Adrian Conlon c8ac0f20dc Step can be split a little to make it easier to override. 2024-07-24 17:21:49 +01:00
Adrian Conlon ee584867c2 Modernise some more c# code 2024-07-18 11:38:02 +01:00
Adrian Conlon d80f340081 Simplfy access to Z80 registers 2024-07-04 08:47:53 +01:00
Adrian Conlon 0c8ed57b0d Add easy to use Register16 assignment methods 2024-07-01 23:27:35 +01:00
Adrian Conlon 38c4c2972c More Word optimisations 2024-06-30 16:04:15 +01:00
Adrian Conlon 1a9b6d3db6 More "Word" optimisations 2024-06-30 14:36:32 +01:00
Adrian Conlon d8fad7b988 Try to minimise use of "Word" from Register16 2024-06-30 12:30:07 +01:00
Adrian Conlon 9979606757 Small performance/readability mod 2024-06-29 18:36:54 +01:00
Adrian Conlon 6e46c8e47f Rationalise use of "intermediate" Register16 2024-06-29 13:38:55 +01:00
Adrian Conlon a64f370d7c Compilation fixes 2024-05-29 10:56:16 +01:00
Adrian Conlon e0235f396e IDE suggestions 2024-05-19 09:07:20 +01:00
Adrian Conlon 47ecdad3e8 Work towards accurate bus/memory/io timings. Especially Z80 m-cycle timing. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2020-07-05 00:09:51 +01:00
Adrian Conlon cd4af67177 Work my way through a bunch of the analysis suggestions. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2020-06-22 00:00:15 +01:00
Adrian Conlon 2becf0e220 Apply any analysis suggestions. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-12-04 23:23:48 +00:00
Adrian Conlon c15ec96862 Make the Z80 implementation M-Cycle accurate. I think! 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-30 14:06:38 +00:00
Adrian Conlon c7c9963db3 Actually, the refresh register is incremented halfway through M1, as the M1 pin is raised. i.e. just before the refresh phase of the M1 cycle. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-16 22:29:42 +00:00
Adrian Conlon ac56257558 Whoops: Z80: missed raising the INT pin, after it been acknowledged. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-16 20:58:52 +00:00
Adrian Conlon 5575fec896 Add Z80 support for the RFRSH pin, triggered by M1 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-16 20:56:08 +00:00
Adrian Conlon a5598942a7 Sync with C++ z80 implementation 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-10 11:17:47 +00:00
Adrian Conlon 0f2a69509b Sync (as far as possible) with unmanaged C++ emulators. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-10-31 23:01:47 +00:00
Adrian Conlon 8ce71f8ab8 Sync with latest C++ version. Fixes a couple of Z80 issues. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-09-08 16:41:04 +01:00
Adrian Conlon f01e3e0430 Tighten up the sequence associated with changing pin levels + fix persistent HALT/PC bug 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-09-06 22:50:21 +01:00
Adrian Conlon bc491884b0 Synchronise HALT implementation for Intel style processors with the C++ version. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-08-29 09:05:31 +01:00
Adrian Conlon 364d79fde9 Correct Z80 halt interrupt bug. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-08-28 23:28:01 +01:00