Adrian Conlon
|
c7c9963db3
|
Actually, the refresh register is incremented halfway through M1, as the M1 pin is raised. i.e. just before the refresh phase of the M1 cycle.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-11-16 22:29:42 +00:00 |
|
Adrian Conlon
|
ac56257558
|
Whoops: Z80: missed raising the INT pin, after it been acknowledged.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-11-16 20:58:52 +00:00 |
|
Adrian Conlon
|
5575fec896
|
Add Z80 support for the RFRSH pin, triggered by M1
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-11-16 20:56:08 +00:00 |
|
Adrian Conlon
|
a5598942a7
|
Sync with C++ z80 implementation
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-11-10 11:17:47 +00:00 |
|
Adrian Conlon
|
0f2a69509b
|
Sync (as far as possible) with unmanaged C++ emulators.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-10-31 23:01:47 +00:00 |
|
Adrian Conlon
|
8ce71f8ab8
|
Sync with latest C++ version. Fixes a couple of Z80 issues.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-09-08 16:41:04 +01:00 |
|
Adrian Conlon
|
f01e3e0430
|
Tighten up the sequence associated with changing pin levels + fix persistent HALT/PC bug
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-09-06 22:50:21 +01:00 |
|
Adrian Conlon
|
bc491884b0
|
Synchronise HALT implementation for Intel style processors with the C++ version.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-29 09:05:31 +01:00 |
|
Adrian Conlon
|
364d79fde9
|
Correct Z80 halt interrupt bug.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-28 23:28:01 +01:00 |
|
Adrian Conlon
|
0dd6f1025f
|
Simplify 8080/Z80 XHTL implementation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-28 23:18:08 +01:00 |
|
Adrian Conlon
|
6c20f49c05
|
Fuse fixes: Missed one of the indexed indirect memory register updates: Whoops!
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-15 17:23:34 +01:00 |
|
Adrian Conlon
|
f07f184ce9
|
Fuse fixes: Correct address high part of output port block writes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-15 16:21:35 +01:00 |
|
Adrian Conlon
|
8db6c6fde9
|
Fuse fixes: Don't write garbage after displaced index arithmetic operation. Damn!
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-15 15:50:28 +01:00 |
|
Adrian Conlon
|
e35dabd130
|
Fuse fixes: Correct bus read/write order of XHTL
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-15 14:31:23 +01:00 |
|
Adrian Conlon
|
d15d1e0d08
|
Start incorporating "event" support into the Fuse tests. Only supported by the Z80 fuse tests at present.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-14 22:38:47 +01:00 |
|
Adrian Conlon
|
f54ef07057
|
Couple of small refactorings, based on repeated bit patterns
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-07 13:27:03 +01:00 |
|
Adrian Conlon
|
853b6e2b08
|
Correct some straightforward analysis issues.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-07-01 00:15:25 +01:00 |
|
Adrian Conlon
|
1d976e811d
|
Introduce a little consistency with regards to pin naming and usage.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2019-04-23 00:58:33 +01:00 |
|
Adrian Conlon
|
e80963260d
|
Try to avoid copying around Register16 references, if possible.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-03-07 01:21:00 +00:00 |
|
Adrian Conlon
|
56f46a8236
|
Speed up Z80 block operations by using values rather than reference objects, if possible.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-03-07 00:28:39 +00:00 |
|
Adrian Conlon
|
12969dbef6
|
Use intermediate values for HL2, if possible.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-02-23 10:38:29 +00:00 |
|
Adrian Conlon
|
03caba99dc
|
Follow most of the guideline suggestions from VS2019 preview. Pretty good suggestions!
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-02-22 22:33:51 +00:00 |
|
Adrian Conlon
|
28b7a88f0f
|
Use the correct virtual methods: BusRead and BusWrite to control bus access for Z80 a la M6502 implementation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-02-22 19:59:42 +00:00 |
|
Adrian Conlon
|
27e1c5c9f8
|
Make Register16 a class, rather than struct. Tricky, but a bit faster than before.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-02-21 19:58:49 +00:00 |
|
Adrian Conlon
|
c0aa7c5ff5
|
Correct a few small mistakes in the Z80 emulation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-02-21 01:10:17 +00:00 |
|
Adrian Conlon
|
c7feb58815
|
Correct a Z80 compare mistake: the result of the implied subtraction shouldn't be applied to the flags register!
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-02-21 00:02:31 +00:00 |
|
Adrian Conlon
|
f0d5751949
|
Fix Z80 LDIR
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-02-20 22:35:22 +00:00 |
|
Adrian Conlon
|
5714798756
|
Lots of stylecop encouraged changes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-02-19 00:56:16 +00:00 |
|
Adrian Conlon
|
ea82c58777
|
Add Z80 processor (untested, but complete)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-02-16 21:32:34 +00:00 |
|